ShellPkg: Use DOS format end of line.

[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / Pci.c

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
index d07ae1721d8b55e7df97d98d05fca384d4a037b4..4a8a97b94f2aae0913597d1aa0f812fb568f3064 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
@@ -1,8 +1,9 @@
 /** @file\r
   Main file for Pci shell Debug1 function.\r
 \r
-  Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
-  Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>\r
+  (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -20,7 +21,6 @@
 #include <IndustryStandard/Acpi.h>\r
 #include "Pci.h"\r
 \r
-#define PCI_CLASS_STRING_LIMIT  54\r
 //\r
 // Printable strings for Pci class code\r
 //\r
@@ -63,9 +63,19 @@ PCI_CLASS_ENTRY PCISubClass_0e[];
 PCI_CLASS_ENTRY PCISubClass_0f[];\r
 PCI_CLASS_ENTRY PCISubClass_10[];\r
 PCI_CLASS_ENTRY PCISubClass_11[];\r
+PCI_CLASS_ENTRY PCISubClass_12[];\r
+PCI_CLASS_ENTRY PCISubClass_13[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
@@ -76,6 +86,8 @@ PCI_CLASS_ENTRY PCIPIFClass_0803[];
 PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
 PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
 \r
 //\r
@@ -172,6 +184,16 @@ PCI_CLASS_ENTRY gClassStringList[] = {
     L"Data Acquisition & Signal Processing Controllers",\r
     PCISubClass_11\r
   },\r
+  {\r
+    0x12,\r
+    L"Processing Accelerators",\r
+    PCISubClass_12\r
+  },\r
+  {\r
+    0x13,\r
+    L"Non-Essential Instrumentation",\r
+    PCISubClass_13\r
+  },\r
   {\r
     0xff,\r
     L"Device does not fit in any defined classes",\r
@@ -221,8 +243,8 @@ PCI_CLASS_ENTRY PCISubClass_00[] = {
 PCI_CLASS_ENTRY PCISubClass_01[] = {\r
   {\r
     0x00,\r
-    L"SCSI controller",\r
-    PCIBlankEntry\r
+    L"SCSI",\r
+    PCIPIFClass_0100\r
   },\r
   {\r
     0x01,\r
@@ -244,6 +266,31 @@ PCI_CLASS_ENTRY PCISubClass_01[] = {
     L"RAID controller",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x05,\r
+    L"ATA controller with ADMA interface",\r
+    PCIPIFClass_0105\r
+  },\r
+  {\r
+    0x06,\r
+    L"Serial ATA controller",\r
+    PCIPIFClass_0106\r
+  },\r
+  {\r
+    0x07,\r
+    L"Serial Attached SCSI (SAS) controller ",\r
+    PCIPIFClass_0107\r
+  },\r
+  {\r
+    0x08,\r
+    L"Non-volatile memory subsystem",\r
+    PCIPIFClass_0108\r
+  },\r
+  {\r
+    0x09,\r
+    L"Universal Flash Storage (UFS) controller ",\r
+    PCIPIFClass_0109\r
+  },\r
   {\r
     0x80,\r
     L"Other mass storage controller",\r
@@ -282,6 +329,21 @@ PCI_CLASS_ENTRY PCISubClass_02[] = {
     L"ISDN controller",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x05,\r
+    L"WorldFip controller",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x06,\r
+    L"PICMG 2.14 Multi Computing",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x07,\r
+    L"InfiniBand controller",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other network controller",\r
@@ -338,6 +400,11 @@ PCI_CLASS_ENTRY PCISubClass_04[] = {
     L"Computer Telephony device",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x03,\r
+    L"Mixed mode device",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other multimedia device",\r
@@ -419,6 +486,21 @@ PCI_CLASS_ENTRY PCISubClass_06[] = {
     L"RACEway bridge",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x09,\r
+    L"Semi-transparent PCI-to-PCI bridge",\r
+    PCIPIFClass_0609\r
+  },\r
+  {\r
+    0x0A,\r
+    L"InfiniBand-to-PCI host bridge",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x0B,\r
+    L"Advanced Switching to PCI host bridge",\r
+    PCIPIFClass_060b\r
+  },\r
   {\r
     0x80,\r
     L"Other bridge type",\r
@@ -452,6 +534,16 @@ PCI_CLASS_ENTRY PCISubClass_07[] = {
     L"Modem",\r
     PCIPIFClass_0703\r
   },\r
+  {\r
+    0x04,\r
+    L"GPIB (IEEE 488.1/2) controller",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x05,\r
+    L"Smart Card",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other communication device",\r
@@ -490,6 +582,21 @@ PCI_CLASS_ENTRY PCISubClass_08[] = {
     L"Generic PCI Hot-Plug controller",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x05,\r
+    L"SD Host controller",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x06,\r
+    L"IOMMU",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x07,\r
+    L"Root Complex Event Collector",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other system peripheral",\r
@@ -609,8 +716,8 @@ PCI_CLASS_ENTRY PCISubClass_0b[] = {
 PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
   {\r
     0x00,\r
-    L"Firewire(IEEE 1394)",\r
-    PCIPIFClass_0c03\r
+    L"IEEE 1394",\r
+    PCIPIFClass_0c00\r
   },\r
   {\r
     0x01,\r
@@ -625,7 +732,7 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = {
   {\r
     0x03,\r
     L"USB",\r
-    PCIPIFClass_0c00\r
+    PCIPIFClass_0c03\r
   },\r
   {\r
     0x04,\r
@@ -637,6 +744,26 @@ PCI_CLASS_ENTRY PCISubClass_0c[] = {
     L"System Management Bus",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x06,\r
+    L"InfiniBand",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x07,\r
+    L"IPMI",\r
+    PCIPIFClass_0c07\r
+  },\r
+  {\r
+    0x08,\r
+    L"SERCOS Interface Standard (IEC 61491)",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x09,\r
+    L"CANbus",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other bus type",\r
@@ -657,14 +784,34 @@ PCI_CLASS_ENTRY PCISubClass_0d[] = {
   },\r
   {\r
     0x01,\r
-    L"Consumer IR controller",\r
-    PCIBlankEntry\r
+    L"",\r
+    PCIPIFClass_0d01\r
   },\r
   {\r
     0x10,\r
     L"RF controller",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x11,\r
+    L"Bluetooth",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x12,\r
+    L"Broadband",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x20,\r
+    L"Ethernet (802.11a - 5 GHz)",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x21,\r
+    L"Ethernet (802.11b - 2.4 GHz)",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other type of wireless controller",\r
@@ -692,25 +839,30 @@ PCI_CLASS_ENTRY PCISubClass_0e[] = {
 \r
 PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
   {\r
-    0x00,\r
+    0x01,\r
     L"TV",\r
     PCIBlankEntry\r
   },\r
   {\r
-    0x01,\r
+    0x02,\r
     L"Audio",\r
     PCIBlankEntry\r
   },\r
   {\r
-    0x02,\r
+    0x03,\r
     L"Voice",\r
     PCIBlankEntry\r
   },\r
   {\r
-    0x03,\r
+    0x04,\r
     L"Data",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x80,\r
+    L"Other satellite communication controller",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x00,\r
     NULL,\r
@@ -747,6 +899,21 @@ PCI_CLASS_ENTRY PCISubClass_11[] = {
     L"DPIO modules",\r
     PCIBlankEntry\r
   },\r
+  {\r
+    0x01,\r
+    L"Performance Counters",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x10,\r
+    L"Communications synchronization plus time and frequency test/measurement ",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x20,\r
+    L"Management card",\r
+    PCIBlankEntry\r
+  },\r
   {\r
     0x80,\r
     L"Other DAQ & SP controllers",\r
@@ -759,9 +926,68 @@ PCI_CLASS_ENTRY PCISubClass_11[] = {
   }\r
 };\r
 \r
+PCI_CLASS_ENTRY PCISubClass_12[] = {\r
+  {\r
+    0x00,\r
+    L"Processing Accelerator",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCISubClass_13[] = {\r
+  {\r
+    0x00,\r
+    L"Non-Essential Instrumentation Function",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
 //\r
 // Programming Interface entries\r
 //\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
+  {\r
+    0x00,\r
+    L"SCSI controller",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x11,\r
+    L"SCSI storage device SOP using PQI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x12,\r
+    L"SCSI controller SOP using PQI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x13,\r
+    L"SCSI storage device and controller SOP using PQI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x21,\r
+    L"SCSI storage device SOP using NVMe",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
 PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
   {\r
     0x00,\r
@@ -930,6 +1156,106 @@ PCI_CLASS_ENTRY PCIPIFClass_0101[] = {
   }\r
 };\r
 \r
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
+  {\r
+    0x20,\r
+    L"Single stepping",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x30,\r
+    L"Continuous operation",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
+  {\r
+    0x00,\r
+    L"",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"AHCI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x02,\r
+    L"Serial Storage Bus",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
+  {\r
+    0x00,\r
+    L"",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"Obsolete",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
+  {\r
+    0x00,\r
+    L"",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"NVMHCI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x02,\r
+    L"NVM Express",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
+  {\r
+    0x00,\r
+    L"",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"UFSHCI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
 PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
   {\r
     0x00,\r
@@ -966,6 +1292,42 @@ PCI_CLASS_ENTRY PCIPIFClass_0604[] = {
   }\r
 };\r
 \r
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
+  {\r
+    0x40,\r
+    L"Primary PCI bus side facing the system host processor",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x80,\r
+    L"Secondary PCI bus side facing the system host processor",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
+  {\r
+    0x00,\r
+    L"Custom",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"ASI-SIG Defined Portal",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
 PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
   {\r
     0x00,\r
@@ -1198,12 +1560,40 @@ PCI_CLASS_ENTRY PCIPIFClass_0904[] = {
 PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
   {\r
     0x00,\r
-    L"Universal Host Controller spec",\r
+    L"",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x10,\r
+    L"Using 1394 OpenHCI spec",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+  {\r
+    0x00,\r
+    L"UHCI",\r
     PCIBlankEntry\r
   },\r
   {\r
     0x10,\r
-    L"Open Host Controller spec",\r
+    L"OHCI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x20,\r
+    L"EHCI",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x30,\r
+    L"xHCI",\r
     PCIBlankEntry\r
   },\r
   {\r
@@ -1223,15 +1613,38 @@ PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {
   }\r
 };\r
 \r
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
   {\r
     0x00,\r
-    L"",\r
+    L"SMIC",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x01,\r
+    L"Keyboard Controller Style",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x02,\r
+    L"Block Transfer",\r
+    PCIBlankEntry\r
+  },\r
+  {\r
+    0x00,\r
+    NULL,\r
+    /* null string ends the list */NULL\r
+  }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
+  {\r
+    0x00,\r
+    L"Consumer IR controller",\r
     PCIBlankEntry\r
   },\r
   {\r
     0x10,\r
-    L"Using 1394 OpenHCI spec",\r
+    L"UWB Radio controller",\r
     PCIBlankEntry\r
   },\r
   {\r
@@ -1378,7 +1791,7 @@ PciGetClassStrings (
   Print strings that represent PCI device class, subclass and programmed I/F.\r
 \r
   @param[in] ClassCodePtr   Points to the memory which stores register Class Code in PCI\r
-                 configuation space.\r
+                            configuration space.\r
   @param[in] IncludePIF     If the printed string should include the programming I/F part\r
 **/\r
 VOID\r
@@ -1391,9 +1804,9 @@ PciPrintClassCode (
   PCI_CLASS_STRINGS ClassStrings;\r
 \r
   ClassCode = 0;\r
-  ClassCode |= ClassCodePtr[0];\r
-  ClassCode |= (ClassCodePtr[1] << 8);\r
-  ClassCode |= (ClassCodePtr[2] << 16);\r
+  ClassCode |= (UINT32)ClassCodePtr[0];\r
+  ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
+  ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
 \r
   //\r
   // Get name from class code\r
@@ -1492,6 +1905,7 @@ PciGetNextBusRange (
   @param[in] ConfigSpace     Data in PCI configuration space.\r
   @param[in] Address         Address used to access configuration space of this PCI device.\r
   @param[in] IoDev           Handle used to access configuration space of PCI device.\r
+  @param[in] EnhancedDump    The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The command completed successfully.\r
 **/\r
@@ -1618,11 +2032,12 @@ PciExplainBridgeControl (
 /**\r
   Print each capability structure.\r
 \r
-  @param[in] IoDev      The pointer to the deivce.\r
-  @param[in] Address    The address to start at.\r
-  @param[in] CapPtr     The offset from the address.\r
+  @param[in] IoDev            The pointer to the deivce.\r
+  @param[in] Address          The address to start at.\r
+  @param[in] CapPtr           The offset from the address.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
 \r
-  @retval EFI_SUCCESS     The operation was successful.\r
+  @retval EFI_SUCCESS         The operation was successful.\r
 **/\r
 EFI_STATUS\r
 PciExplainCapabilityStruct (\r
@@ -1635,9 +2050,13 @@ PciExplainCapabilityStruct (
 /**\r
   Display Pcie device structure.\r
 \r
-  @param[in] IoDev          The pointer to the root pci protocol.\r
-  @param[in] Address        The Address to start at.\r
-  @param[in] CapabilityPtr  The offset from the address to start.\r
+  @param[in] IoDev            The pointer to the root pci protocol.\r
+  @param[in] Address          The Address to start at.\r
+  @param[in] CapabilityPtr    The offset from the address to start.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
+  \r
+  @retval EFI_SUCCESS           The command completed successfully.\r
+  @retval @retval EFI_SUCCESS   Pci express extend space IO is not suppoted.   \r
 **/\r
 EFI_STATUS\r
 PciExplainPciExpress (\r
@@ -1656,7 +2075,7 @@ PciExplainPciExpress (
 **/\r
 EFI_STATUS\r
 ExplainPcieCapReg (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1668,7 +2087,7 @@ ExplainPcieCapReg (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1680,7 +2099,7 @@ ExplainPcieDeviceCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1692,7 +2111,7 @@ ExplainPcieDeviceControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1704,7 +2123,7 @@ ExplainPcieDeviceStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1716,7 +2135,7 @@ ExplainPcieLinkCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1728,7 +2147,7 @@ ExplainPcieLinkControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1740,7 +2159,7 @@ ExplainPcieLinkStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1752,7 +2171,7 @@ ExplainPcieSlotCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1764,7 +2183,7 @@ ExplainPcieSlotControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1776,7 +2195,7 @@ ExplainPcieSlotStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1788,7 +2207,7 @@ ExplainPcieRootControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
 /**\r
@@ -1800,10 +2219,10 @@ ExplainPcieRootCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   );\r
 \r
-typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
+typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r
 \r
 typedef enum {\r
   FieldWidthUINT8,\r
@@ -2077,7 +2496,7 @@ ShellCommandRunPci (
   Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
   if (EFI_ERROR(Status)) {\r
     if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam);  \r
       FreePool(ProblemParam);\r
       ShellStatus = SHELL_INVALID_PARAMETER;\r
     } else {\r
@@ -2086,18 +2505,18 @@ ShellCommandRunPci (
   } else {\r
 \r
     if (ShellCommandLineGetCount(Package) == 2) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci");  \r
       ShellStatus = SHELL_INVALID_PARAMETER;\r
       goto Done;\r
     }\r
 \r
     if (ShellCommandLineGetCount(Package) > 4) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci");  \r
       ShellStatus = SHELL_INVALID_PARAMETER;\r
       goto Done;\r
     }\r
     if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle,  L"pci", L"-s");  \r
       ShellStatus = SHELL_INVALID_PARAMETER;\r
       goto Done;\r
     }\r
@@ -2109,7 +2528,7 @@ ShellCommandRunPci (
     HandleBufSize = sizeof (EFI_HANDLE);\r
     HandleBuf     = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
     if (HandleBuf == NULL) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");  \r
       ShellStatus = SHELL_OUT_OF_RESOURCES;\r
       goto Done;\r
     }\r
@@ -2125,7 +2544,7 @@ ShellCommandRunPci (
     if (Status == EFI_BUFFER_TOO_SMALL) {\r
       HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
       if (HandleBuf == NULL) {\r
-        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci");  \r
         ShellStatus = SHELL_OUT_OF_RESOURCES;\r
         goto Done;\r
       }\r
@@ -2140,7 +2559,7 @@ ShellCommandRunPci (
     }\r
 \r
     if (EFI_ERROR (Status)) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci");  \r
       ShellStatus = SHELL_NOT_FOUND;\r
       goto Done;\r
     }\r
@@ -2176,7 +2595,7 @@ ShellCommandRunPci (
                   &Descriptors\r
                  );\r
         if (EFI_ERROR (Status)) {\r
-          ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
+          ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci");  \r
           ShellStatus = SHELL_NOT_FOUND;\r
           goto Done;\r
         }\r
@@ -2189,7 +2608,7 @@ ShellCommandRunPci (
           Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
 \r
           if (EFI_ERROR (Status)) {\r
-            ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
+            ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci");  \r
             ShellStatus = SHELL_NOT_FOUND;\r
             goto Done;\r
           }\r
@@ -2313,7 +2732,7 @@ ShellCommandRunPci (
       if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
         Segment = (UINT16) RetVal;\r
       } else {\r
-        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
@@ -2331,13 +2750,13 @@ ShellCommandRunPci (
       if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
         Bus = (UINT16) RetVal;\r
       } else {\r
-        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
 \r
       if (Bus > MAX_BUS_NUMBER) {\r
-        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
@@ -2350,13 +2769,13 @@ ShellCommandRunPci (
       if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
         Device = (UINT16) RetVal;\r
       } else {\r
-        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
 \r
       if (Device > MAX_DEVICE_NUMBER){\r
-        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
@@ -2370,13 +2789,13 @@ ShellCommandRunPci (
       if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
         Func = (UINT16) RetVal;\r
       } else {\r
-        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+        ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
 \r
       if (Func > MAX_FUNCTION_NUMBER){\r
-        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+        ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp);  \r
         ShellStatus = SHELL_INVALID_PARAMETER;\r
         goto Done;\r
       }\r
@@ -2396,7 +2815,7 @@ ShellCommandRunPci (
 \r
     if (EFI_ERROR (Status)) {\r
       ShellPrintHiiEx(\r
-        -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
+        -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci",  \r
         Segment,\r
         Bus\r
        );\r
@@ -2414,7 +2833,7 @@ ShellCommandRunPci (
                          );\r
 \r
     if (EFI_ERROR (Status)) {\r
-      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
+      ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci");  \r
       ShellStatus = SHELL_ACCESS_DENIED;\r
       goto Done;\r
     }\r
@@ -2660,6 +3079,7 @@ PciGetNextBusRange (
   @param[in] ConfigSpace     Data in PCI configuration space.\r
   @param[in] Address         Address used to access configuration space of this PCI device.\r
   @param[in] IoDev           Handle used to access configuration space of PCI device.\r
+  @param[in] EnhancedDump    The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The command completed successfully.\r
 **/\r
@@ -3790,9 +4210,10 @@ PciExplainBridgeControl (
 /**\r
   Print each capability structure.\r
 \r
-  @param[in] IoDev      The pointer to the deivce.\r
-  @param[in] Address    The address to start at.\r
-  @param[in] CapPtr     The offset from the address.\r
+  @param[in] IoDev            The pointer to the deivce.\r
+  @param[in] Address          The address to start at.\r
+  @param[in] CapPtr           The offset from the address.\r
+  @param[in] EnhancedDump     The print format for the dump data.\r
 \r
   @retval EFI_SUCCESS     The operation was successful.\r
 **/\r
@@ -3845,7 +4266,7 @@ PciExplainCapabilityStruct (
 **/\r
 EFI_STATUS\r
 ExplainPcieCapReg (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieCapReg;\r
@@ -3893,7 +4314,7 @@ ExplainPcieCapReg (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieCapReg;\r
@@ -3982,7 +4403,7 @@ ExplainPcieDeviceCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieCapReg;\r
@@ -4059,7 +4480,7 @@ ExplainPcieDeviceControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieDeviceStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieDeviceStatus;\r
@@ -4101,7 +4522,7 @@ ExplainPcieDeviceStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT32 PcieLinkCap;\r
@@ -4192,7 +4613,7 @@ ExplainPcieLinkCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieLinkControl;\r
@@ -4263,7 +4684,7 @@ ExplainPcieLinkControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieLinkStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieLinkStatus;\r
@@ -4324,7 +4745,7 @@ ExplainPcieLinkStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT32 PcieSlotCap;\r
@@ -4392,7 +4813,7 @@ ExplainPcieSlotCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieSlotControl;\r
@@ -4456,7 +4877,7 @@ ExplainPcieSlotControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieSlotStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieSlotStatus;\r
@@ -4517,7 +4938,7 @@ ExplainPcieSlotStatus (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootControl (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieRootControl;\r
@@ -4557,7 +4978,7 @@ ExplainPcieRootControl (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootCap (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT16 PcieRootCap;\r
@@ -4581,7 +5002,7 @@ ExplainPcieRootCap (
 **/\r
 EFI_STATUS\r
 ExplainPcieRootStatus (\r
-  IN PCIE_CAP_STURCTURE *PciExpressCap\r
+  IN PCIE_CAP_STRUCTURE *PciExpressCap\r
   )\r
 {\r
   UINT32 PcieRootStatus;\r
@@ -5023,7 +5444,10 @@ PrintInterpretedExtendedCompatibilityAer (
     Header->CorrectableErrorStatus,\r
     Header->CorrectableErrorMask,\r
     Header->AdvancedErrorCapabilitiesAndControl,\r
-    Header->HeaderLog,\r
+    Header->HeaderLog[0],\r
+    Header->HeaderLog[1],\r
+    Header->HeaderLog[2],\r
+    Header->HeaderLog[3],\r
     Header->RootErrorCommand,\r
     Header->RootErrorStatus,\r
     Header->ErrorSourceIdentification,\r
@@ -5054,7 +5478,7 @@ EFIAPI
 PrintInterpretedExtendedCompatibilityMulticast (\r
   IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
   IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
-  IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
   )\r
 {\r
   CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
@@ -5226,7 +5650,7 @@ EFIAPI
 PrintInterpretedExtendedCompatibilitySecondary (\r
   IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
   IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
-  IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
   )\r
 {\r
   CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
@@ -5268,7 +5692,7 @@ EFIAPI
 PrintPciExtendedCapabilityDetails(\r
   IN CONST PCI_EXP_EXT_HDR    *HeadersBaseAddress, \r
   IN CONST PCI_EXP_EXT_HDR    *HeaderAddress,\r
-  IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+  IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
   )\r
 {\r
   switch (HeaderAddress->CapabilityId){\r
@@ -5326,6 +5750,8 @@ PrintPciExtendedCapabilityDetails(
   @param[in] IoDev          The pointer to the root pci protocol.\r
   @param[in] Address        The Address to start at.\r
   @param[in] CapabilityPtr  The offset from the address to start.\r
+  @param[in] EnhancedDump   The print format for the dump data.\r
+  \r
 **/\r
 EFI_STATUS\r
 PciExplainPciExpress (\r
@@ -5336,7 +5762,7 @@ PciExplainPciExpress (
   )\r
 {\r
 \r
-  PCIE_CAP_STURCTURE  PciExpressCap;\r
+  PCIE_CAP_STRUCTURE  PciExpressCap;\r
   EFI_STATUS          Status;\r
   UINT64              CapRegAddress;\r
   UINT8               Bus;\r