/** @file\r
Main file for Pci shell Debug1 function.\r
\r
- Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
+ (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>\r
Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
#include <IndustryStandard/Acpi.h>\r
#include "Pci.h"\r
\r
-#define PCI_CLASS_STRING_LIMIT 54\r
//\r
// Printable strings for Pci class code\r
//\r
PCI_CLASS_ENTRY PCISubClass_0f[];\r
PCI_CLASS_ENTRY PCISubClass_10[];\r
PCI_CLASS_ENTRY PCISubClass_11[];\r
+PCI_CLASS_ENTRY PCISubClass_12[];\r
+PCI_CLASS_ENTRY PCISubClass_13[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[];\r
PCI_CLASS_ENTRY PCIPIFClass_0101[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[];\r
PCI_CLASS_ENTRY PCIPIFClass_0300[];\r
PCI_CLASS_ENTRY PCIPIFClass_0604[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[];\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[];\r
PCI_CLASS_ENTRY PCIPIFClass_0700[];\r
PCI_CLASS_ENTRY PCIPIFClass_0701[];\r
PCI_CLASS_ENTRY PCIPIFClass_0703[];\r
PCI_CLASS_ENTRY PCIPIFClass_0904[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[];\r
PCI_CLASS_ENTRY PCIPIFClass_0c03[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[];\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[];\r
PCI_CLASS_ENTRY PCIPIFClass_0e00[];\r
\r
//\r
L"Data Acquisition & Signal Processing Controllers",\r
PCISubClass_11\r
},\r
+ {\r
+ 0x12,\r
+ L"Processing Accelerators",\r
+ PCISubClass_12\r
+ },\r
+ {\r
+ 0x13,\r
+ L"Non-Essential Instrumentation",\r
+ PCISubClass_13\r
+ },\r
{\r
0xff,\r
L"Device does not fit in any defined classes",\r
PCI_CLASS_ENTRY PCISubClass_01[] = {\r
{\r
0x00,\r
- L"SCSI controller",\r
- PCIBlankEntry\r
+ L"SCSI",\r
+ PCIPIFClass_0100\r
},\r
{\r
0x01,\r
L"RAID controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"ATA controller with ADMA interface",\r
+ PCIPIFClass_0105\r
+ },\r
+ {\r
+ 0x06,\r
+ L"Serial ATA controller",\r
+ PCIPIFClass_0106\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Serial Attached SCSI (SAS) controller ",\r
+ PCIPIFClass_0107\r
+ },\r
+ {\r
+ 0x08,\r
+ L"Non-volatile memory subsystem",\r
+ PCIPIFClass_0108\r
+ },\r
+ {\r
+ 0x09,\r
+ L"Universal Flash Storage (UFS) controller ",\r
+ PCIPIFClass_0109\r
+ },\r
{\r
0x80,\r
L"Other mass storage controller",\r
L"ISDN controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"WorldFip controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"PICMG 2.14 Multi Computing",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"InfiniBand controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other network controller",\r
L"Computer Telephony device",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x03,\r
+ L"Mixed mode device",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other multimedia device",\r
L"RACEway bridge",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x09,\r
+ L"Semi-transparent PCI-to-PCI bridge",\r
+ PCIPIFClass_0609\r
+ },\r
+ {\r
+ 0x0A,\r
+ L"InfiniBand-to-PCI host bridge",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x0B,\r
+ L"Advanced Switching to PCI host bridge",\r
+ PCIPIFClass_060b\r
+ },\r
{\r
0x80,\r
L"Other bridge type",\r
L"Modem",\r
PCIPIFClass_0703\r
},\r
+ {\r
+ 0x04,\r
+ L"GPIB (IEEE 488.1/2) controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x05,\r
+ L"Smart Card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other communication device",\r
L"Generic PCI Hot-Plug controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x05,\r
+ L"SD Host controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x06,\r
+ L"IOMMU",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"Root Complex Event Collector",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other system peripheral",\r
PCI_CLASS_ENTRY PCISubClass_0c[] = {\r
{\r
0x00,\r
- L"Firewire(IEEE 1394)",\r
- PCIPIFClass_0c03\r
+ L"IEEE 1394",\r
+ PCIPIFClass_0c00\r
},\r
{\r
0x01,\r
{\r
0x03,\r
L"USB",\r
- PCIPIFClass_0c00\r
+ PCIPIFClass_0c03\r
},\r
{\r
0x04,\r
L"System Management Bus",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x06,\r
+ L"InfiniBand",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x07,\r
+ L"IPMI",\r
+ PCIPIFClass_0c07\r
+ },\r
+ {\r
+ 0x08,\r
+ L"SERCOS Interface Standard (IEC 61491)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x09,\r
+ L"CANbus",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other bus type",\r
},\r
{\r
0x01,\r
- L"Consumer IR controller",\r
- PCIBlankEntry\r
+ L"",\r
+ PCIPIFClass_0d01\r
},\r
{\r
0x10,\r
L"RF controller",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x11,\r
+ L"Bluetooth",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"Broadband",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Ethernet (802.11a - 5 GHz)",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"Ethernet (802.11b - 2.4 GHz)",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other type of wireless controller",\r
\r
PCI_CLASS_ENTRY PCISubClass_0f[] = {\r
{\r
- 0x00,\r
+ 0x01,\r
L"TV",\r
PCIBlankEntry\r
},\r
{\r
- 0x01,\r
+ 0x02,\r
L"Audio",\r
PCIBlankEntry\r
},\r
{\r
- 0x02,\r
+ 0x03,\r
L"Voice",\r
PCIBlankEntry\r
},\r
{\r
- 0x03,\r
+ 0x04,\r
L"Data",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x80,\r
+ L"Other satellite communication controller",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x00,\r
NULL,\r
L"DPIO modules",\r
PCIBlankEntry\r
},\r
+ {\r
+ 0x01,\r
+ L"Performance Counters",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Communications synchronization plus time and frequency test/measurement ",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"Management card",\r
+ PCIBlankEntry\r
+ },\r
{\r
0x80,\r
L"Other DAQ & SP controllers",\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCISubClass_12[] = {\r
+ {\r
+ 0x00,\r
+ L"Processing Accelerator",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCISubClass_13[] = {\r
+ {\r
+ 0x00,\r
+ L"Non-Essential Instrumentation Function",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
//\r
// Programming Interface entries\r
//\r
+PCI_CLASS_ENTRY PCIPIFClass_0100[] = {\r
+ {\r
+ 0x00,\r
+ L"SCSI controller",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x11,\r
+ L"SCSI storage device SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x12,\r
+ L"SCSI controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x13,\r
+ L"SCSI storage device and controller SOP using PQI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x21,\r
+ L"SCSI storage device SOP using NVMe",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0101[] = {\r
{\r
0x00,\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCIPIFClass_0105[] = {\r
+ {\r
+ 0x20,\r
+ L"Single stepping",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x30,\r
+ L"Continuous operation",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0106[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"AHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Serial Storage Bus",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0107[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Obsolete",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0108[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"NVMHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"NVM Express",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0109[] = {\r
+ {\r
+ 0x00,\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"UFSHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0300[] = {\r
{\r
0x00,\r
}\r
};\r
\r
+PCI_CLASS_ENTRY PCIPIFClass_0609[] = {\r
+ {\r
+ 0x40,\r
+ L"Primary PCI bus side facing the system host processor",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x80,\r
+ L"Secondary PCI bus side facing the system host processor",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_060b[] = {\r
+ {\r
+ 0x00,\r
+ L"Custom",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"ASI-SIG Defined Portal",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
PCI_CLASS_ENTRY PCIPIFClass_0700[] = {\r
{\r
0x00,\r
PCI_CLASS_ENTRY PCIPIFClass_0c00[] = {\r
{\r
0x00,\r
- L"Universal Host Controller spec",\r
+ L"",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x10,\r
+ L"Using 1394 OpenHCI spec",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+ {\r
+ 0x00,\r
+ L"UHCI",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Open Host Controller spec",\r
+ L"OHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x20,\r
+ L"EHCI",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x30,\r
+ L"xHCI",\r
PCIBlankEntry\r
},\r
{\r
}\r
};\r
\r
-PCI_CLASS_ENTRY PCIPIFClass_0c03[] = {\r
+PCI_CLASS_ENTRY PCIPIFClass_0c07[] = {\r
{\r
0x00,\r
- L"",\r
+ L"SMIC",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x01,\r
+ L"Keyboard Controller Style",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x02,\r
+ L"Block Transfer",\r
+ PCIBlankEntry\r
+ },\r
+ {\r
+ 0x00,\r
+ NULL,\r
+ /* null string ends the list */NULL\r
+ }\r
+};\r
+\r
+PCI_CLASS_ENTRY PCIPIFClass_0d01[] = {\r
+ {\r
+ 0x00,\r
+ L"Consumer IR controller",\r
PCIBlankEntry\r
},\r
{\r
0x10,\r
- L"Using 1394 OpenHCI spec",\r
+ L"UWB Radio controller",\r
PCIBlankEntry\r
},\r
{\r
Print strings that represent PCI device class, subclass and programmed I/F.\r
\r
@param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI\r
- configuation space.\r
+ configuration space.\r
@param[in] IncludePIF If the printed string should include the programming I/F part\r
**/\r
VOID\r
PCI_CLASS_STRINGS ClassStrings;\r
\r
ClassCode = 0;\r
- ClassCode |= ClassCodePtr[0];\r
- ClassCode |= (ClassCodePtr[1] << 8);\r
- ClassCode |= (ClassCodePtr[2] << 16);\r
+ ClassCode |= (UINT32)ClassCodePtr[0];\r
+ ClassCode |= (UINT32)(ClassCodePtr[1] << 8);\r
+ ClassCode |= (UINT32)(ClassCodePtr[2] << 16);\r
\r
//\r
// Get name from class code\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
/**\r
Print each capability structure.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
\r
- @retval EFI_SUCCESS The operation was successful.\r
+ @retval EFI_SUCCESS The operation was successful.\r
**/\r
EFI_STATUS\r
PciExplainCapabilityStruct (\r
/**\r
Display Pcie device structure.\r
\r
- @param[in] IoDev The pointer to the root pci protocol.\r
- @param[in] Address The Address to start at.\r
- @param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] IoDev The pointer to the root pci protocol.\r
+ @param[in] Address The Address to start at.\r
+ @param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
+ \r
+ @retval EFI_SUCCESS The command completed successfully.\r
+ @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted. \r
**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
);\r
\r
-typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STURCTURE *PciExpressCap);\r
+typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION) (IN PCIE_CAP_STRUCTURE *PciExpressCap);\r
\r
typedef enum {\r
FieldWidthUINT8,\r
Status = ShellCommandLineParse (ParamList, &Package, &ProblemParam, TRUE);\r
if (EFI_ERROR(Status)) {\r
if (Status == EFI_VOLUME_CORRUPTED && ProblemParam != NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, ProblemParam);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, L"pci", ProblemParam); \r
FreePool(ProblemParam);\r
ShellStatus = SHELL_INVALID_PARAMETER;\r
} else {\r
} else {\r
\r
if (ShellCommandLineGetCount(Package) == 2) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_FEW), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (ShellCommandLineGetCount(Package) > 4) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_TOO_MANY), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (ShellCommandLineGetFlag(Package, L"-s") && ShellCommandLineGetValue(Package, L"-s") == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"-s");\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_NO_VALUE), gShellDebug1HiiHandle, L"pci", L"-s"); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
HandleBufSize = sizeof (EFI_HANDLE);\r
HandleBuf = (EFI_HANDLE *) AllocateZeroPool (HandleBufSize);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
if (Status == EFI_BUFFER_TOO_SMALL) {\r
HandleBuf = ReallocatePool (sizeof (EFI_HANDLE), HandleBufSize, HandleBuf);\r
if (HandleBuf == NULL) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_OUT_MEM), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_OUT_OF_RESOURCES;\r
goto Done;\r
}\r
}\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PCIRBIO_NF), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
&Descriptors\r
);\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
Status = PciGetNextBusRange (&Descriptors, &MinBus, &MaxBus, &IsEnd);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_NOT_FOUND;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Segment = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Bus = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Bus > MAX_BUS_NUMBER) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Device = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Device > MAX_DEVICE_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
if (!EFI_ERROR (ShellConvertStringToUint64 (Temp, &RetVal, TRUE, TRUE))) {\r
Func = (UINT16) RetVal;\r
} else {\r
- ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle);\r
+ ShellPrintHiiEx (-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV_HEX), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (Func > MAX_FUNCTION_NUMBER){\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PROBLEM), gShellDebug1HiiHandle, Temp);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_GEN_PARAM_INV), gShellDebug1HiiHandle, L"pci", Temp); \r
ShellStatus = SHELL_INVALID_PARAMETER;\r
goto Done;\r
}\r
\r
if (EFI_ERROR (Status)) {\r
ShellPrintHiiEx(\r
- -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle,\r
+ -1, -1, NULL, STRING_TOKEN (STR_PCI_NO_FIND), gShellDebug1HiiHandle, L"pci", \r
Segment,\r
Bus\r
);\r
);\r
\r
if (EFI_ERROR (Status)) {\r
- ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, Status);\r
+ ShellPrintHiiEx(-1, -1, NULL, STRING_TOKEN (STR_PCI_NO_CFG), gShellDebug1HiiHandle, L"pci"); \r
ShellStatus = SHELL_ACCESS_DENIED;\r
goto Done;\r
}\r
@param[in] ConfigSpace Data in PCI configuration space.\r
@param[in] Address Address used to access configuration space of this PCI device.\r
@param[in] IoDev Handle used to access configuration space of PCI device.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
\r
@retval EFI_SUCCESS The command completed successfully.\r
**/\r
/**\r
Print each capability structure.\r
\r
- @param[in] IoDev The pointer to the deivce.\r
- @param[in] Address The address to start at.\r
- @param[in] CapPtr The offset from the address.\r
+ @param[in] IoDev The pointer to the deivce.\r
+ @param[in] Address The address to start at.\r
+ @param[in] CapPtr The offset from the address.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
\r
@retval EFI_SUCCESS The operation was successful.\r
**/\r
**/\r
EFI_STATUS\r
ExplainPcieCapReg (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieCapReg;\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieCapReg;\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieCapReg;\r
**/\r
EFI_STATUS\r
ExplainPcieDeviceStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieDeviceStatus;\r
**/\r
EFI_STATUS\r
ExplainPcieLinkCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT32 PcieLinkCap;\r
**/\r
EFI_STATUS\r
ExplainPcieLinkControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieLinkControl;\r
**/\r
EFI_STATUS\r
ExplainPcieLinkStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieLinkStatus;\r
**/\r
EFI_STATUS\r
ExplainPcieSlotCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT32 PcieSlotCap;\r
**/\r
EFI_STATUS\r
ExplainPcieSlotControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieSlotControl;\r
**/\r
EFI_STATUS\r
ExplainPcieSlotStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieSlotStatus;\r
**/\r
EFI_STATUS\r
ExplainPcieRootControl (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieRootControl;\r
**/\r
EFI_STATUS\r
ExplainPcieRootCap (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT16 PcieRootCap;\r
**/\r
EFI_STATUS\r
ExplainPcieRootStatus (\r
- IN PCIE_CAP_STURCTURE *PciExpressCap\r
+ IN PCIE_CAP_STRUCTURE *PciExpressCap\r
)\r
{\r
UINT32 PcieRootStatus;\r
return (EFI_SUCCESS);\r
}\r
\r
+/**\r
+ Function to interpret and print out the multicast structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityMulticast (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST), \r
+ gShellDebug1HiiHandle, \r
+ Header->MultiCastCapability,\r
+ Header->MulticastControl,\r
+ Header->McBaseAddress,\r
+ Header->McReceiveAddress,\r
+ Header->McBlockAll,\r
+ Header->McBlockUntranslated,\r
+ Header->McOverlayBar\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the virtual channel and multi virtual channel structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityVirtualChannel (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY *Header;\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC *CapabilityItem;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE), \r
+ gShellDebug1HiiHandle, \r
+ Header->ExtendedVcCount,\r
+ Header->PortVcCapability1,\r
+ Header->PortVcCapability2,\r
+ Header->VcArbTableOffset,\r
+ Header->PortVcControl,\r
+ Header->PortVcStatus\r
+ );\r
+ for (ItemCount = 0 ; ItemCount < Header->ExtendedVcCount ; ItemCount++) {\r
+ CapabilityItem = &Header->Capability[ItemCount];\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ CapabilityItem->VcResourceCapability,\r
+ CapabilityItem->PortArbTableOffset,\r
+ CapabilityItem->VcResourceControl,\r
+ CapabilityItem->VcResourceStatus\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC) + (Header->ExtendedVcCount - 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the resizeable bar structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityResizeableBar (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR *Header;\r
+ UINT32 ItemCount;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR*)HeaderAddress;\r
+\r
+ for (ItemCount = 0 ; ItemCount < (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) ; ItemCount++) {\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR), \r
+ gShellDebug1HiiHandle, \r
+ ItemCount+1,\r
+ Header->Capability[ItemCount].ResizableBarCapability,\r
+ Header->Capability[ItemCount].ResizableBarControl\r
+ );\r
+ }\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ (UINT32)GET_NUMBER_RESIZABLE_BARS(Header) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the TPH structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilityTph (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_TPH), \r
+ gShellDebug1HiiHandle, \r
+ Header->TphRequesterCapability,\r
+ Header->TphRequesterControl\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->TphStTable - (UINT8*)HeadersBaseAddress),\r
+ GET_TPH_TABLE_SIZE(Header),\r
+ (VOID *)Header->TphStTable\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) + GET_TPH_TABLE_SIZE(Header) - sizeof(UINT16),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
+/**\r
+ Function to interpret and print out the secondary PCIe capability structure\r
+\r
+ @param[in] HeaderAddress The Address of this capability header.\r
+ @param[in] HeadersBaseAddress The address of all the extended capability headers.\r
+ @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PrintInterpretedExtendedCompatibilitySecondary (\r
+ IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
+ IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress,\r
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
+ )\r
+{\r
+ CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE *Header;\r
+ Header = (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE*)HeaderAddress;\r
+\r
+ ShellPrintHiiEx(\r
+ -1, -1, NULL, \r
+ STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY), \r
+ gShellDebug1HiiHandle, \r
+ Header->LinkControl3,\r
+ Header->LaneErrorStatus\r
+ );\r
+ DumpHex (\r
+ 8,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)Header->EqualizationControl - (UINT8*)HeadersBaseAddress),\r
+ PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
+ (VOID *)Header->EqualizationControl\r
+ );\r
+\r
+ DumpHex (\r
+ 4,\r
+ EFI_PCIE_CAPABILITY_BASE_OFFSET + ((UINT8*)HeaderAddress - (UINT8*)HeadersBaseAddress),\r
+ sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH) - sizeof(Header->EqualizationControl) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr->LinkCap),\r
+ (VOID *) (HeaderAddress)\r
+ );\r
+\r
+ return (EFI_SUCCESS);\r
+}\r
+\r
/**\r
Display Pcie extended capability details\r
\r
PrintPciExtendedCapabilityDetails(\r
IN CONST PCI_EXP_EXT_HDR *HeadersBaseAddress, \r
IN CONST PCI_EXP_EXT_HDR *HeaderAddress,\r
- IN CONST PCIE_CAP_STURCTURE *PciExpressCapPtr\r
+ IN CONST PCIE_CAP_STRUCTURE *PciExpressCapPtr\r
)\r
{\r
switch (HeaderAddress->CapabilityId){\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID:\r
return PrintInterpretedExtendedCompatibilityAer(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID:\r
return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID:\r
return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID:\r
return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID:\r
return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID:\r
return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID:\r
return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID:\r
return PrintInterpretedExtendedCompatibilityAri(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID:\r
return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID:\r
return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID:\r
return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress, HeadersBaseAddress);\r
- break;\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID:\r
return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress, HeadersBaseAddress);\r
- break;\r
-/**\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID:\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID:\r
- ASSERT(FALSE);\r
- break;\r
+ return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress, HeadersBaseAddress);\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID: \r
-// use PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
- ASSERT(FALSE);\r
- break;\r
+ //\r
+ // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b\r
+ //\r
+ return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID:\r
- ASSERT(FALSE);\r
- break;\r
+ return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress, HeadersBaseAddress);\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID:\r
- ASSERT(FALSE);\r
- break;\r
+ return PrintInterpretedExtendedCompatibilityTph(HeaderAddress, HeadersBaseAddress);\r
case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID:\r
- // use PciExpressCapPtr link capabilities register\r
- ASSERT(FALSE);\r
- break;\r
-//**/\r
+ return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress, HeadersBaseAddress, PciExpressCapPtr);\r
default:\r
ShellPrintEx (-1, -1,\r
L"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",\r
HeaderAddress->CapabilityId\r
);\r
return EFI_SUCCESS;\r
- break;\r
};\r
\r
}\r
@param[in] IoDev The pointer to the root pci protocol.\r
@param[in] Address The Address to start at.\r
@param[in] CapabilityPtr The offset from the address to start.\r
+ @param[in] EnhancedDump The print format for the dump data.\r
+ \r
**/\r
EFI_STATUS\r
PciExplainPciExpress (\r
)\r
{\r
\r
- PCIE_CAP_STURCTURE PciExpressCap;\r
+ PCIE_CAP_STRUCTURE PciExpressCap;\r
EFI_STATUS Status;\r
UINT64 CapRegAddress;\r
UINT8 Bus;\r
projects / mirror_edk2.git / blobdiff