ShellPkg: Update header file including style

[mirror_edk2.git] / ShellPkg / Library / UefiShellDebug1CommandsLib / SmbiosView / PrintInfo.h

diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
index d9bf3b687de070defbc16029ab471363479be1b4..1aa5bee08f092cb54f28907a31f0efc627b706b7 100644 (file)
--- a/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
+++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/PrintInfo.h
@@ -1,7 +1,8 @@
 /** @file\r
   Module to clarify the element info of the smbios structure.\r
 \r
-  Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved.<BR>\r
+  (C) Copyright 2017 Hewlett Packard Enterprise Development LP<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -15,7 +16,7 @@
 #ifndef _SMBIOS_PRINT_INFO_H_\r
 #define _SMBIOS_PRINT_INFO_H_\r
 \r
-#include "LibSmbios.h"\r
+#include <IndustryStandard/SmBios.h>\r
 \r
 extern UINT8  SmbiosMajorVersion;\r
 extern UINT8  SmbiosMinorVersion;\r
@@ -42,8 +43,20 @@ extern UINT8  SmbiosMinorVersion;
 **/\r
 VOID\r
 SmbiosPrintEPSInfo (\r
-  IN  SMBIOS_STRUCTURE_TABLE  *SmbiosTable,\r
-  IN  UINT8                   Option\r
+  IN  SMBIOS_TABLE_ENTRY_POINT  *SmbiosTable,\r
+  IN  UINT8                     Option\r
+  );\r
+\r
+/**\r
+  Print the info of 64-bit EPS(Entry Point Structure).\r
+\r
+  @param[in] SmbiosTable    Pointer to the SMBIOS table entry point.\r
+  @param[in] Option         Display option.\r
+**/\r
+VOID\r
+Smbios64BitPrintEPSInfo (\r
+  IN  SMBIOS_TABLE_3_0_ENTRY_POINT  *SmbiosTable,\r
+  IN  UINT8                         Option\r
   );\r
 \r
 /**\r
@@ -154,19 +167,19 @@ DisplayProcessorVoltage (
   Display processor information.\r
 \r
   @param[in] Status   The status.\r
-                        Bit 7 Reserved, must be 0\r
-                        Bit 6   CPU Socket Populated\r
-                         1 - CPU Socket Populated\r
-                         0 - CPU Socket UnpopulatedBits\r
-                         5:3  Reserved, must be zero\r
-                         Bits 2:0 CPU Status\r
-                          0h - Unknown\r
-                          1h - CPU Enabled\r
-                          2h - CPU Disabled by User via BIOS Setup\r
-                          3h - CPU Disabled By BIOS (POST Error)\r
-                          4h - CPU is Idle, waiting to be enabled.\r
-                          5-6h - Reserved\r
-                          7h - Other\r
+Bit 7 Reserved, must be 0\r
+Bit 6 CPU Socket Populated\r
+  1 - CPU Socket Populated\r
+  0 - CPU Socket Unpopulated\r
+Bits 5:3 Reserved, must be zero\r
+Bits 2:0 CPU Status\r
+  0h - Unknown\r
+  1h - CPU Enabled\r
+  2h - CPU Disabled by User via BIOS Setup\r
+  3h - CPU Disabled By BIOS (POST Error)\r
+  4h - CPU is Idle, waiting to be enabled.\r
+  5-6h - Reserved\r
+  7h - Other\r
 \r
   @param[in] Option   The option\r
 **/\r
@@ -236,6 +249,40 @@ DisplayMmMemorySize (
   IN UINT8 Option\r
   );\r
 \r
+/**\r
+  Display Cache Configuration.\r
+\r
+  @param[in] CacheConfiguration   Cache Configuration.\r
+Bits 15:10 Reserved, must be 0\r
+Bits 9:8 Operational Mode\r
+  0h - Write Through\r
+  1h - Write Back\r
+  2h - Varies with Memory Address\r
+  3h - Unknown\r
+Bit 7 Enabled/Disabled\r
+  1 - Enabled\r
+  0 - Disabled\r
+Bits 6:5 Location\r
+  0h - Internal\r
+  1h - External\r
+  2h - Reserved\r
+  3h - Unknown\r
+Bit 4 Reserved, must be zero\r
+Bit 3 Cache Socketed\r
+  1 - Socketed\r
+  0 - Unsocketed\r
+Bits 2:0 Cache Level\r
+  1 through 8 (For example, an L1 cache would\r
+  use value 000b and an L3 cache would use 010b.)\r
+\r
+  @param[in] Option   The option\r
+**/\r
+VOID\r
+DisplayCacheConfiguration (\r
+  IN UINT16 CacheConfiguration,\r
+  IN UINT8 Option\r
+  );\r
+\r
 /**\r
   The Slot ID field of the System Slot structure provides a mechanism to\r
   correlate the physical attributes of the slot to its logical access method\r
@@ -374,4 +421,16 @@ DisplaySPSCharacteristics (
   IN UINT8   Option\r
   );\r
 \r
+/**\r
+  Display TPM Device (Type 43) Characteristics.\r
+\r
+  @param[in] Chara    The information bits.\r
+  @param[in] Option   The optional information.\r
+**/\r
+VOID\r
+DisplayTpmDeviceCharacteristics (\r
+  IN UINT64  Chara,\r
+  IN UINT8   Option\r
+  );\r
+\r
 #endif\r