//\r
// CPU I/O 2 Protocol instance\r
//\r
-EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
+EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
{\r
CpuMemoryServiceRead,\r
CpuMemoryServiceWrite\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mInStride[] = {\r
+UINT8 mInStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
-UINT8 mOutStride[] = {\r
+UINT8 mOutStride[] = {\r
1, // EfiCpuIoWidthUint8\r
2, // EfiCpuIoWidthUint16\r
4, // EfiCpuIoWidthUint32\r
// For FIFO type, the target address won't increase during the access,\r
// so treat Count as 1\r
//\r
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {\r
Count = 1;\r
}\r
\r
//\r
// Check to see if Width is in the valid range for I/O Port operations\r
//\r
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
if (MaxCount < (Count - 1)) {\r
return EFI_UNSUPPORTED;\r
}\r
+\r
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
return EFI_UNSUPPORTED;\r
}\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = MmioRead8 ((UINTN)Address);\r
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
}\r
}\r
+\r
return EFI_SUCCESS;\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
//\r
// Fifo operations supported for (mInStride[Width] == 0)\r
//\r
if (InStride == 0) {\r
switch (OperationWidth) {\r
- case EfiCpuIoWidthUint8:\r
- IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint16:\r
- IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint32:\r
- IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
+ case EfiCpuIoWidthUint8:\r
+ IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
\r
//\r
// Select loop based on the width of the transfer\r
//\r
- InStride = mInStride[Width];\r
- OutStride = mOutStride[Width];\r
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+ InStride = mInStride[Width];\r
+ OutStride = mOutStride[Width];\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
\r
//\r
// Fifo operations supported for (mInStride[Width] == 0)\r
//\r
if (InStride == 0) {\r
switch (OperationWidth) {\r
- case EfiCpuIoWidthUint8:\r
- IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint16:\r
- IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- case EfiCpuIoWidthUint32:\r
- IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
- return EFI_SUCCESS;\r
- default:\r
- //\r
- // The CpuIoCheckParameter call above will ensure that this\r
- // path is not taken.\r
- //\r
- ASSERT (FALSE);\r
- break;\r
+ case EfiCpuIoWidthUint8:\r
+ IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
}\r
}\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
&mHandle,\r
- &gEfiCpuIo2ProtocolGuid, &mCpuIo2,\r
+ &gEfiCpuIo2ProtocolGuid,\r
+ &mCpuIo2,\r
NULL\r
);\r
ASSERT_EFI_ERROR (Status);\r