/** @file\r
Produces the CPU I/O 2 Protocol.\r
\r
-Copyright (c) 2009 - 2010, Intel Corporation\r
-All rights reserved. This program and the accompanying materials \r
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
+This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
http://opensource.org/licenses/bsd-license.php \r
\r
**/\r
\r
-#include <PiDxe.h>\r
-\r
-#include <Protocol/CpuIo2.h>\r
-\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/UefiBootServicesTableLib.h>\r
-\r
-#define MAX_IO_PORT_ADDRESS 0xFFFF\r
-\r
-//\r
-// Function Prototypes\r
-//\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceRead (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMemoryServiceWrite (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceRead (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- OUT VOID *Buffer\r
- );\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-CpuIoServiceWrite (\r
- IN EFI_CPU_IO2_PROTOCOL *This,\r
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r
- IN UINT64 Address,\r
- IN UINTN Count,\r
- IN VOID *Buffer\r
- );\r
+#include "CpuIo2Dxe.h"\r
\r
//\r
// Handle for the CPU I/O 2 Protocol\r
//\r
// Check to see if Width is in the valid range\r
//\r
- if (Width < 0 || Width >= EfiCpuIoWidthMaximum) {\r
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
// Check to see if Width is in the valid range for I/O Port operations\r
//\r
- Width = Width & 0x03;\r
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
//\r
- // Check to see if Address is alligned\r
+ // Check to see if Address is aligned\r
//\r
- if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
+ if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
// can also be the maximum integer value supported by the CPU, this range\r
// check must be adjusted to avoid all oveflow conditions.\r
// \r
- // The follwing form of the range check is equivalent but assumes that \r
+ // The following form of the range check is equivalent but assumes that \r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
//\r
Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
}\r
\r
//\r
- // Check to see if Buffer is alligned\r
+ // Check to see if Buffer is aligned\r
+ // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)\r
//\r
- if (((UINTN)Buffer & (mInStride[Width] - 1)) != 0) {\r
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {\r
return EFI_UNSUPPORTED;\r
}\r
\r
//\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
- OperationWidth = Width & 0x03;\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = MmioRead8 ((UINTN)Address);\r
//\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
- OperationWidth = Width & 0x03;\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
//\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
- OperationWidth = Width & 0x03;\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+\r
+ //\r
+ // Fifo operations supported for (mInStride[Width] == 0)\r
+ //\r
+ if (InStride == 0) {\r
+ switch (OperationWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+\r
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
*Uint8Buffer = IoRead8 ((UINTN)Address);\r
//\r
InStride = mInStride[Width];\r
OutStride = mOutStride[Width];\r
- OperationWidth = Width & 0x03;\r
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+\r
+ //\r
+ // Fifo operations supported for (mInStride[Width] == 0)\r
+ //\r
+ if (InStride == 0) {\r
+ switch (OperationWidth) {\r
+ case EfiCpuIoWidthUint8:\r
+ IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint16:\r
+ IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ case EfiCpuIoWidthUint32:\r
+ IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+ return EFI_SUCCESS;\r
+ default:\r
+ //\r
+ // The CpuIoCheckParameter call above will ensure that this\r
+ // path is not taken.\r
+ //\r
+ ASSERT (FALSE);\r
+ break;\r
+ }\r
+ }\r
+\r
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
if (OperationWidth == EfiCpuIoWidthUint8) {\r
IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
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