Local APIC library assumes local APIC is enabled. It does not\r
handles cases where local APIC is disabled.\r
\r
- Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.\r
#define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.\r
\r
+/**\r
+ Retrieve the base address of local APIC.\r
+\r
+ @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Set the base address of local APIC.\r
+\r
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+ @param[in] BaseAddress Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+ IN UINTN BaseAddress\r
+ );\r
+\r
/**\r
Get the current local APIC mode.\r
\r
If the specified local APIC mode can't be set as current, then ASSERT.\r
\r
@param ApicMode APIC mode to be set.\r
+\r
+ @note This API must not be called from an interrupt handler or SMI handler.\r
+ It may result in unpredictable behavior.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
- In xAPIC mode, the initial local APIC ID is 8-bit, and may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
VOID\r
);\r
\r
+/**\r
+ Get the value of the local APIC version register.\r
+\r
+ @return the value of the local APIC version register.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetApicVersion (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Send a Fixed IPI to a specified target processor.\r
+\r
+ This function returns after the IPI has been accepted by the target processor.\r
+\r
+ @param ApicId The local APIC ID of the target processor.\r
+ @param Vector The vector number of the interrupt being sent.\r
+**/\r
+VOID\r
+EFIAPI\r
+SendFixedIpi (\r
+ IN UINT32 ApicId,\r
+ IN UINT8 Vector\r
+ );\r
+\r
+/**\r
+ Send a Fixed IPI to all processors excluding self.\r
+\r
+ This function returns after the IPI has been accepted by the target processors.\r
+\r
+ @param Vector The vector number of the interrupt being sent.\r
+**/\r
+VOID\r
+EFIAPI\r
+SendFixedIpiAllExcludingSelf (\r
+ IN UINT8 Vector\r
+ );\r
+\r
/**\r
Send a SMI IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send a SMI IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT IPI to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
@param ApicId Specify the local APIC ID of the target processor.\r
**/\r
/**\r
Send an INIT IPI to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
**/\r
VOID\r
EFIAPI\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r
\r
- This function returns after the IPI has been accepted by the target processor. \r
+ This function returns after the IPI has been accepted by the target processor.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
/**\r
Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r
\r
- This function returns after the IPI has been accepted by the target processors. \r
+ This function returns after the IPI has been accepted by the target processors.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
IN UINT32 StartupRoutine\r
);\r
\r
+/**\r
+ Initialize the state of the SoftwareEnable bit in the Local APIC\r
+ Spurious Interrupt Vector register.\r
+\r
+ @param Enable If TRUE, then set SoftwareEnable to 1\r
+ If FALSE, then set SoftwareEnable to 0.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeLocalApicSoftwareEnable (\r
+ IN BOOLEAN Enable\r
+ );\r
+\r
/**\r
Programming Virtual Wire Mode.\r
\r
);\r
\r
/**\r
- Get the divide value from the DCR (Divide Configuration Register) by which\r
- the processor's bus clock is divided to form the time base for the APIC timer.\r
+ Disable LINT0 & LINT1 interrupts.\r
\r
- @return The divide value is one of 1,2,4,8,16,32,64,128.\r
+ This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r
**/\r
-UINTN\r
+VOID\r
EFIAPI\r
-GetApicTimerDivisor (\r
+DisableLvtInterrupts (\r
VOID\r
);\r
\r
IN UINT8 Vector\r
);\r
\r
+/**\r
+ Get the state of the local APIC timer.\r
+\r
+ @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r
+ @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r
+ @param Vector Return the timer interrupt vector number.\r
+**/\r
+VOID\r
+EFIAPI\r
+GetApicTimerState (\r
+ OUT UINTN *DivideValue OPTIONAL,\r
+ OUT BOOLEAN *PeriodicMode OPTIONAL,\r
+ OUT UINT8 *Vector OPTIONAL\r
+ );\r
+\r
/**\r
Enable the local APIC timer interrupt.\r
**/\r
VOID\r
);\r
\r
+/**\r
+ Get the 32-bit address that a device should use to send a Message Signaled\r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI\r
+GetApicMsiAddress (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get the 64-bit data value that a device should use to send a Message Signaled\r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ If Vector is not in range 0x10..0xFE, then ASSERT().\r
+ If DeliveryMode is not supported, then ASSERT().\r
+\r
+ @param Vector The 8-bit interrupt vector associated with the MSI.\r
+ Must be in the range 0x10..0xFE\r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI\r
+ is handled. The only supported values are:\r
+ 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+ 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+ 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+ 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+ 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+ 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+\r
+ @param LevelTriggered TRUE specifies a level triggered interrupt.\r
+ FALSE specifies an edge triggered interrupt.\r
+ @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
+ TRUE specifies a level triggered interrupt that active\r
+ when the interrupt line is asserted.\r
+ FALSE specifies a level triggered interrupt that active\r
+ when the interrupt line is deasserted.\r
+\r
+ @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetApicMsiValue (\r
+ IN UINT8 Vector,\r
+ IN UINTN DeliveryMode,\r
+ IN BOOLEAN LevelTriggered,\r
+ IN BOOLEAN AssertionLevel\r
+ );\r
+\r
+/**\r
+ Get Package ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of logical processors\r
+ per package, number of cores per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+EFIAPI\r
+GetProcessorLocationByApicId (\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ );\r
+\r
+/**\r
+ Get Package ID/Module ID/Tile ID/Die ID/Core ID/Thread ID of a processor.\r
+\r
+ The algorithm assumes the target system has symmetry across physical\r
+ package boundaries with respect to the number of threads per core, number of\r
+ cores per module, number of modules per tile, number of tiles per die, number\r
+ of dies per package.\r
+\r
+ @param[in] InitialApicId Initial APIC ID of the target logical processor.\r
+ @param[out] Package Returns the processor package ID.\r
+ @param[out] Die Returns the processor die ID.\r
+ @param[out] Tile Returns the processor tile ID.\r
+ @param[out] Module Returns the processor module ID.\r
+ @param[out] Core Returns the processor core ID.\r
+ @param[out] Thread Returns the processor thread ID.\r
+**/\r
+VOID\r
+EFIAPI\r
+GetProcessorLocation2ByApicId (\r
+ IN UINT32 InitialApicId,\r
+ OUT UINT32 *Package OPTIONAL,\r
+ OUT UINT32 *Die OPTIONAL,\r
+ OUT UINT32 *Tile OPTIONAL,\r
+ OUT UINT32 *Module OPTIONAL,\r
+ OUT UINT32 *Core OPTIONAL,\r
+ OUT UINT32 *Thread OPTIONAL\r
+ );\r
#endif\r
\r
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