/** @file\r
IA32 Local APIC Definitions.\r
\r
- Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
UINT32 Uint32;\r
} LOCAL_APIC_LVT_LINT;\r
\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Reserved0:2; ///< Reserved\r
+ UINT32 DestinationMode:1; ///< Specifies the Destination Mode.\r
+ UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.\r
+ UINT32 Reserved1:8; ///< Reserved.\r
+ UINT32 DestinationId:8; ///< Specifies the Destination ID.\r
+ UINT32 BaseAddress:12; ///< Must be 0FEEH\r
+ } Bits;\r
+ UINT32 Uint32;\r
+} LOCAL_APIC_MSI_ADDRESS;\r
+\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+ struct {\r
+ UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH\r
+ UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.\r
+ UINT32 Reserved0:3; ///< Reserved.\r
+ UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
+ UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.\r
+ UINT32 Reserved1:16; ///< Reserved.\r
+ UINT32 Reserved2:32; ///< Reserved.\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} LOCAL_APIC_MSI_DATA;\r
+\r
#endif\r
\r