BaseTools: Update sign tool to make MonotonicCount *after* Payload

[mirror_edk2.git] / UefiCpuPkg / Include / Register / LocalApic.h

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 7535ef50e95ef0777b55ddcf0e7bd35be8d11bde..cfb6d76d8b3449244e9c92e790c70dae7d9bd709 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -1,7 +1,7 @@
 /** @file\r
   IA32 Local APIC Definitions.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -15,30 +15,19 @@
 #ifndef __LOCAL_APIC_H__\r
 #define __LOCAL_APIC_H__\r
 \r
-//\r
-// Definitions for IA32 architectural MSRs\r
-//\r
-#define MSR_IA32_APIC_BASE_ADDRESS              0x1B\r
-\r
-//\r
-// Definitions for CPUID instruction\r
-//\r
-#define CPUID_VERSION_INFO                      0x1\r
-#define CPUID_EXTENDED_FUNCTION                 0x80000000\r
-#define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008\r
-\r
 //\r
 // Definition for Local APIC registers and related values\r
 //\r
-#define XAPIC_ID_OFFSET                         0x0\r
+#define XAPIC_ID_OFFSET                         0x20\r
+#define XAPIC_VERSION_OFFSET                    0x30\r
 #define XAPIC_EOI_OFFSET                        0x0b0\r
 #define XAPIC_ICR_DFR_OFFSET                    0x0e0\r
 #define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0\r
 #define XAPIC_ICR_LOW_OFFSET                    0x300\r
 #define XAPIC_ICR_HIGH_OFFSET                   0x310\r
 #define XAPIC_LVT_TIMER_OFFSET                  0x320\r
-#define XAPIC_LINT0_VECTOR_OFFSET               0x350\r
-#define XAPIC_LINT1_VECTOR_OFFSET               0x360\r
+#define XAPIC_LVT_LINT0_OFFSET                  0x350\r
+#define XAPIC_LVT_LINT1_OFFSET                  0x360\r
 #define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380\r
 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390\r
 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
@@ -59,17 +48,19 @@
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
 \r
+//\r
+// Local APIC Version Register.\r
+//\r
 typedef union {\r
   struct {\r
-    UINT64  Reserved0:8;   ///< Reserved.\r
-    UINT64  Bsp:1;         ///< Processor is BSP.\r
-    UINT64  Reserved1:1;   ///< Reserved.\r
-    UINT64  Extd:1;        ///< Enable x2APIC mode.\r
-    UINT64  En:1;          ///< xAPIC global enable/disable.\r
-    UINT64  ApicBase:52;   ///< APIC Base physical address. The actual field width depends on physical address width.\r
+    UINT32  Version:8;                  ///< The version numbers of the local APIC.\r
+    UINT32  Reserved0:8;                ///< Reserved.\r
+    UINT32  MaxLvtEntry:8;              ///< Number of LVT entries minus 1.\r
+    UINT32  EoiBroadcastSuppression:1;  ///< 1 if EOI-broadcast suppression supported.\r
+    UINT32  Reserved1:7;                ///< Reserved.\r
   } Bits;\r
-  UINT64    Uint64;\r
-} MSR_IA32_APIC_BASE;\r
+  UINT32    Uint32;\r
+} LOCAL_APIC_VERSION;\r
 \r
 //\r
 // Low half of Interrupt Command Register (ICR).\r
@@ -163,5 +154,36 @@ typedef union {
   UINT32    Uint32;\r
 } LOCAL_APIC_LVT_LINT;\r
 \r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Reserved0:2;         ///< Reserved\r
+    UINT32  DestinationMode:1;   ///< Specifies the Destination Mode.\r
+    UINT32  RedirectionHint:1;   ///< Specifies the Redirection Hint.\r
+    UINT32  Reserved1:8;         ///< Reserved.\r
+    UINT32  DestinationId:8;     ///< Specifies the Destination ID.\r
+    UINT32  BaseAddress:12;      ///< Must be 0FEEH\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} LOCAL_APIC_MSI_ADDRESS;\r
+\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Vector:8;            ///< Interrupt vector in range 010h..0FEH\r
+    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.\r
+    UINT32  Reserved0:3;         ///< Reserved.\r
+    UINT32  Level:1;             ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.\r
+    UINT32  TriggerMode:1;       ///< 0:Edge,     1:Level.\r
+    UINT32  Reserved1:16;        ///< Reserved.\r
+    UINT32  Reserved2:32;        ///< Reserved.\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} LOCAL_APIC_MSI_DATA;\r
+\r
 #endif\r
 \r