\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.\r
\r
**/\r
\r
\r
\r
/**\r
- Unique. Last Branch Record 0 From IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction . See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
\r
@param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Unique. Last Branch Record 0 To IP (R/W) One of eight pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last eight\r
- branches, exceptions, or interrupts taken by the processor.\r
+ Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r
+ record registers on the last branch record stack. The To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 35-2. Default value is 0.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_ATOM_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_ATOM_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_ATOM_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
-/**\r
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r
} MSR_ATOM_PEBS_ENABLE_REGISTER;\r
\r
\r
-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC3_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_CTL 0x00000410\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC4_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC4_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_ADDR 0x00000412\r
-\r
-\r
/**\r
Package. Package C2 Residency Note: C-state values are processor specific\r
C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r
projects / mirror_edk2.git / blobdiff