returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.2.\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel(R) Core(TM) 2 Processor Family?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x0F || \\r
+ DisplayModel == 0x17 \\r
+ ) \\r
+ )\r
+\r
/**\r
Shared. Model Specific Platform ID (R).\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);\r
@endcode\r
+ @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
#define MSR_CORE2_PLATFORM_ID 0x00000017\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);\r
AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
**/\r
#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);\r
AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.\r
**/\r
#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
\r
\r
/**\r
Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the source instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor. See also: -\r
- Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
- Interrupt, and Exception Recording (Pentium M Processors).".\r
+ record registers on the last branch record stack. The From_IP part of the\r
+ stack contains pointers to the source instruction. See also: - Last Branch\r
+ Record Stack TOS at 1C9H - Section 17.5.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);\r
AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);\r
@endcode\r
+ @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r
@{\r
**/\r
#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
\r
/**\r
Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
- record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last four\r
- branches, exceptions, or interrupts taken by the processor.\r
+ record registers on the last branch record stack. This To_IP part of the\r
+ stack contains pointers to the destination instruction.\r
\r
@param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);\r
AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);\r
@endcode\r
+ @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r
+ MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r
@{\r
**/\r
#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
Msr.Uint64 = 0;\r
AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.\r
**/\r
#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
\r
Msr.Uint64 = 0;\r
AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.\r
**/\r
#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);\r
@endcode\r
+ @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r
**/\r
#define MSR_CORE2_FSB_FREQ 0x000000CD\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);\r
AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
**/\r
#define MSR_CORE2_BBL_CR_CTL3 0x0000011E\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);\r
AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r
**/\r
#define MSR_CORE2_PERF_STATUS 0x00000198\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);\r
AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
**/\r
#define MSR_CORE2_THERM2_CTL 0x0000019D\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);\r
AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);\r
AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);\r
@endcode\r
+ @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
\r
\r
Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);\r
@endcode\r
+ @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
\r
\r
Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);\r
@endcode\r
+ @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
\r
Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);\r
AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);\r
@endcode\r
+ @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.\r
+ MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.\r
+ MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.\r
@{\r
**/\r
#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);\r
AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.\r
**/\r
#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
\r
Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);\r
AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);\r
@endcode\r
+ @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.\r
**/\r
#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
\r
\r
-/**\r
- Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
\r
- @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
@param EDX Upper 32-bits of MSR value.\r
\r
@code\r
UINT64 Msr;\r
\r
- Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);\r
@endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_CORE2_PERF_GLOBAL_STATUS 0x0000038E\r
\r
\r
/**\r
Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);\r
AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);\r
@endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
\r
Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);\r
AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);\r
@endcode\r
+ @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
\r
\r
/**\r
- Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling\r
(PEBS).".\r
\r
@param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
\r
} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
\r
\r
-/**\r
- Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC4_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC4_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC4_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC4_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_CORE2_MC3_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC3_CTL 0x00000410\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_CORE2_MC3_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC3_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_CORE2_MC3_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC3_ADDR 0x00000412\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC3_MISC (0x00000413)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC3_MISC 0x00000413\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_CTL (0x00000414)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC5_CTL 0x00000414\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_STATUS (0x00000415)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC5_STATUS 0x00000415\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_ADDR (0x00000416)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC5_ADDR 0x00000416\r
-\r
-\r
-/**\r
- Unique.\r
-\r
- @param ECX MSR_CORE2_MC5_MISC (0x00000417)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);\r
- AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC5_MISC 0x00000417\r
-\r
-\r
-/**\r
- Unique. Apply to Intel Xeon processor 7400 series (processor signature\r
- 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.\r
-\r
- @param ECX MSR_CORE2_MC6_STATUS (0x00000419)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);\r
- AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);\r
- @endcode\r
-**/\r
-#define MSR_CORE2_MC6_STATUS 0x00000419\r
-\r
-\r
/**\r
Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);\r
AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);\r
@endcode\r
+ @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r
+ MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r
@{\r
**/\r
#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);\r
AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);\r
@endcode\r
+ @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.\r
**/\r
#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
\r
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