UefiCpuPkg/Msr: Add CPUID signature check MACROs

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / HaswellMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index f7cb6ce39f92717b3e70f5778b06b2579d09e8c3..3cd15846b4fd2e19d8eb64d01c5265589faa52f3 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -17,7 +17,7 @@
 \r
   @par Specification Reference:\r
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.\r
+  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.\r
 \r
 **/\r
 \r
@@ -26,6 +26,24 @@
 \r
 #include <Register/ArchitecturalMsr.h>\r
 \r
+/**\r
+  Is Intel processors based on the Haswell microarchitecture?\r
+\r
+  @param   DisplayFamily  Display Family ID\r
+  @param   DisplayModel   Display Model ID\r
+\r
+  @retval  TRUE   Yes, it is.\r
+  @retval  FALSE  No, it isn't.\r
+**/\r
+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
+  (DisplayFamily == 0x06 && \\r
+   (                        \\r
+    DisplayModel == 0x3C || \\r
+    DisplayModel == 0x45 || \\r
+    DisplayModel == 0x46    \\r
+    )                       \\r
+   )\r
+\r
 /**\r
   Package.\r
 \r
@@ -442,15 +460,8 @@ typedef union {
     UINT32  InterruptResponseTimeLimit:10;\r
     ///\r
     /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time\r
-    /// unit of the interrupt response time limit. The following time unit\r
-    /// encodings are supported:\r
-    ///\r
-    ///   000b: 1 ns\r
-    ///   001b: 32 ns\r
-    ///   010b: 1024 ns\r
-    ///   011b: 32768 ns\r
-    ///   100b: 1048576 ns\r
-    ///   101b: 33554432 ns.\r
+    /// unit of the interrupt response time limit. See Table 35-18 for\r
+    /// supported time unit encodings.\r
     ///\r
     UINT32  TimeUnit:3;\r
     UINT32  Reserved1:2;\r
@@ -514,15 +525,8 @@ typedef union {
     UINT32  InterruptResponseTimeLimit:10;\r
     ///\r
     /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time\r
-    /// unit of the interrupt response time limit. The following time unit\r
-    /// encodings are supported:\r
-    ///\r
-    ///   000b: 1 ns\r
-    ///   001b: 32 ns\r
-    ///   010b: 1024 ns\r
-    ///   011b: 32768 ns\r
-    ///   100b: 1048576 ns\r
-    ///   101b: 33554432 ns.\r
+    /// unit of the interrupt response time limit. See Table 35-18 for\r
+    /// supported time unit encodings.\r
     ///\r
     UINT32  TimeUnit:3;\r
     UINT32  Reserved1:2;\r
@@ -863,25 +867,6 @@ typedef union {
 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
 \r
 \r
-/**\r
-  Package. Silicon Debug Feature Control (R/W) See Table 35-2.\r
-\r
-  @param  ECX  MSR_HASWELL_IA32_DEBUG_FEATURE (0x00000C80)\r
-  @param  EAX  Lower 32-bits of MSR value.\r
-  @param  EDX  Upper 32-bits of MSR value.\r
-\r
-  <b>Example usage</b>\r
-  @code\r
-  UINT64  Msr;\r
-\r
-  Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);\r
-  AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);\r
-  @endcode\r
-  @note MSR_HASWELL_IA32_DEBUG_FEATURE is defined as IA32_DEBUG_FEATURE in SDM.\r
-**/\r
-#define MSR_HASWELL_IA32_DEBUG_FEATURE           0x00000C80\r
-\r
-\r
 /**\r
   Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
   specific C-state code names, unrelated to MWAIT extension C-state parameters\r
@@ -1609,6 +1594,25 @@ typedef union {
 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
 \r
 \r
+/**\r
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL\r
+  Domains.".\r
+\r
+  @param  ECX  MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r
+  @endcode\r
+  @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
+**/\r
+#define MSR_HASWELL_PP0_ENERGY_STATUS            0x00000639\r
+\r
+\r
 /**\r
   Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
   RAPL Domains.".\r