returned is a single 32-bit or 64-bit value, then a data structure is not\r
provided for that MSR.\r
\r
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
\r
@par Specification Reference:\r
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
- December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5.\r
+ September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.6.\r
\r
**/\r
\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
+/**\r
+ Is Intel processors based on the Nehalem microarchitecture?\r
+\r
+ @param DisplayFamily Display Family ID\r
+ @param DisplayModel Display Model ID\r
+\r
+ @retval TRUE Yes, it is.\r
+ @retval FALSE No, it isn't.\r
+**/\r
+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r
+ (DisplayFamily == 0x06 && \\r
+ ( \\r
+ DisplayModel == 0x1A || \\r
+ DisplayModel == 0x1E || \\r
+ DisplayModel == 0x1F || \\r
+ DisplayModel == 0x2E \\r
+ ) \\r
+ )\r
+\r
/**\r
Package. Model Specific Platform ID (R).\r
\r
/// auto-demote information.\r
///\r
UINT32 C1AutoDemotion:1;\r
- UINT32 Reserved4:5;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
UINT32 Reserved5:32;\r
} Bits;\r
///\r
UINT32 Reserved1:2;\r
///\r
/// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
- /// Table 35-2.\r
+ /// Table 35-2. Default value is 1.\r
///\r
UINT32 AutomaticThermalControlCircuit:1;\r
UINT32 Reserved2:3;\r
///\r
UINT32 BTS:1;\r
///\r
- /// [Bit 12] Thread. Precise Event Based Sampling Unavailable (RO) See\r
+ /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
/// Table 35-2.\r
///\r
UINT32 PEBS:1;\r
\r
/**\r
Core. Last Branch Record Filtering Select Register (R/W) See Section\r
- 17.6.2, "Filtering of Last Branch Records.".\r
+ 17.7.2, "Filtering of Last Branch Records.".\r
\r
@param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
@param EAX Lower 32-bits of MSR value.\r
} MSR_NEHALEM_POWER_CTL_REGISTER;\r
\r
\r
-/**\r
- Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
- Facilities.".\r
-\r
- @param ECX MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS is defined as IA32_PERF_GLOBAL_STAUS in SDM.\r
-**/\r
-#define MSR_NEHALEM_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
-\r
-\r
/**\r
Thread. (RO).\r
\r
- @param ECX MSR_NEHALEM_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
@param EAX Lower 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
@param EDX Upper 32-bits of MSR value.\r
- Described by the type MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER.\r
+ Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
\r
<b>Example usage</b>\r
@code\r
- MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER Msr;\r
+ MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;\r
\r
- Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STAUS);\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
@endcode\r
- @note MSR_NEHALEM_PERF_GLOBAL_STAUS is defined as MSR_PERF_GLOBAL_STAUS in SDM.\r
+ @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
-#define MSR_NEHALEM_PERF_GLOBAL_STAUS 0x0000038E\r
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E\r
\r
/**\r
- MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STAUS\r
+ MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
///\r
/// All bit fields as a 64-bit value\r
///\r
UINT64 Uint64;\r
-} MSR_NEHALEM_PERF_GLOBAL_STAUS_REGISTER;\r
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
\r
\r
/**\r
- Thread. See Section 18.7.1.1, "Precise Event Based Sampling (PEBS).".\r
+ Thread. See Section 18.8.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
@param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Thread. See Section 18.7.1.2, "Load Latency Performance Monitoring\r
+ Thread. See Section 18.8.1.2, "Load Latency Performance Monitoring\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
#define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD\r
\r
\r
-/**\r
- See Section 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
-\r
- @param ECX MSR_NEHALEM_MCi_MISC\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC0_MISC);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC0_MISC, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC0_MISC is defined as MSR_MC0_MISC in SDM.\r
- MSR_NEHALEM_MC1_MISC is defined as MSR_MC1_MISC in SDM.\r
- MSR_NEHALEM_MC2_MISC is defined as MSR_MC2_MISC in SDM.\r
- MSR_NEHALEM_MC3_MISC is defined as MSR_MC3_MISC in SDM.\r
- MSR_NEHALEM_MC4_MISC is defined as MSR_MC4_MISC in SDM.\r
- MSR_NEHALEM_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
- MSR_NEHALEM_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
- MSR_NEHALEM_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
- MSR_NEHALEM_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
- MSR_NEHALEM_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
- MSR_NEHALEM_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
- MSR_NEHALEM_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
- MSR_NEHALEM_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
- MSR_NEHALEM_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
- MSR_NEHALEM_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
- MSR_NEHALEM_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
- MSR_NEHALEM_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
- MSR_NEHALEM_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
- MSR_NEHALEM_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
- MSR_NEHALEM_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
- MSR_NEHALEM_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
- MSR_NEHALEM_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC0_MISC 0x00000403\r
-#define MSR_NEHALEM_MC1_MISC 0x00000407\r
-#define MSR_NEHALEM_MC2_MISC 0x0000040B\r
-#define MSR_NEHALEM_MC3_MISC 0x0000040F\r
-#define MSR_NEHALEM_MC4_MISC 0x00000413\r
-#define MSR_NEHALEM_MC5_MISC 0x00000417\r
-#define MSR_NEHALEM_MC6_MISC 0x0000041B\r
-#define MSR_NEHALEM_MC7_MISC 0x0000041F\r
-#define MSR_NEHALEM_MC8_MISC 0x00000423\r
-#define MSR_NEHALEM_MC9_MISC 0x00000427\r
-#define MSR_NEHALEM_MC10_MISC 0x0000042B\r
-#define MSR_NEHALEM_MC11_MISC 0x0000042F\r
-#define MSR_NEHALEM_MC12_MISC 0x00000433\r
-#define MSR_NEHALEM_MC13_MISC 0x00000437\r
-#define MSR_NEHALEM_MC14_MISC 0x0000043B\r
-#define MSR_NEHALEM_MC15_MISC 0x0000043F\r
-#define MSR_NEHALEM_MC16_MISC 0x00000443\r
-#define MSR_NEHALEM_MC17_MISC 0x00000447\r
-#define MSR_NEHALEM_MC18_MISC 0x0000044B\r
-#define MSR_NEHALEM_MC19_MISC 0x0000044F\r
-#define MSR_NEHALEM_MC20_MISC 0x00000453\r
-#define MSR_NEHALEM_MC21_MISC 0x00000457\r
-/// @}\r
-\r
-\r
-/**\r
- See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_NEHALEM_MCi_CTL\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_CTL);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
- MSR_NEHALEM_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
- MSR_NEHALEM_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
- MSR_NEHALEM_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
- MSR_NEHALEM_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
- MSR_NEHALEM_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
- MSR_NEHALEM_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
- MSR_NEHALEM_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
- MSR_NEHALEM_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
- MSR_NEHALEM_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
- MSR_NEHALEM_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
- MSR_NEHALEM_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
- MSR_NEHALEM_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
- MSR_NEHALEM_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
- MSR_NEHALEM_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
- MSR_NEHALEM_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
- MSR_NEHALEM_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
- MSR_NEHALEM_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
- MSR_NEHALEM_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_CTL 0x0000040C\r
-#define MSR_NEHALEM_MC4_CTL 0x00000410\r
-#define MSR_NEHALEM_MC5_CTL 0x00000414\r
-#define MSR_NEHALEM_MC6_CTL 0x00000418\r
-#define MSR_NEHALEM_MC7_CTL 0x0000041C\r
-#define MSR_NEHALEM_MC8_CTL 0x00000420\r
-#define MSR_NEHALEM_MC9_CTL 0x00000424\r
-#define MSR_NEHALEM_MC10_CTL 0x00000428\r
-#define MSR_NEHALEM_MC11_CTL 0x0000042C\r
-#define MSR_NEHALEM_MC12_CTL 0x00000430\r
-#define MSR_NEHALEM_MC13_CTL 0x00000434\r
-#define MSR_NEHALEM_MC14_CTL 0x00000438\r
-#define MSR_NEHALEM_MC15_CTL 0x0000043C\r
-#define MSR_NEHALEM_MC16_CTL 0x00000440\r
-#define MSR_NEHALEM_MC17_CTL 0x00000444\r
-#define MSR_NEHALEM_MC18_CTL 0x00000448\r
-#define MSR_NEHALEM_MC19_CTL 0x0000044C\r
-#define MSR_NEHALEM_MC20_CTL 0x00000450\r
-#define MSR_NEHALEM_MC21_CTL 0x00000454\r
-/// @}\r
-\r
-\r
-/**\r
- See Section 15.3.2.2, "IA32_MCi_STATUS MSRS," and Chapter 16.\r
-\r
- @param ECX MSR_NEHALEM_MCi_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
- MSR_NEHALEM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
- MSR_NEHALEM_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
- MSR_NEHALEM_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
- MSR_NEHALEM_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
- MSR_NEHALEM_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
- MSR_NEHALEM_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
- MSR_NEHALEM_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
- MSR_NEHALEM_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
- MSR_NEHALEM_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
- MSR_NEHALEM_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
- MSR_NEHALEM_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
- MSR_NEHALEM_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
- MSR_NEHALEM_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
- MSR_NEHALEM_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
- MSR_NEHALEM_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
- MSR_NEHALEM_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
- MSR_NEHALEM_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
- MSR_NEHALEM_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_STATUS 0x0000040D\r
-#define MSR_NEHALEM_MC4_STATUS 0x00000411\r
-#define MSR_NEHALEM_MC5_STATUS 0x00000415\r
-#define MSR_NEHALEM_MC6_STATUS 0x00000419\r
-#define MSR_NEHALEM_MC7_STATUS 0x0000041D\r
-#define MSR_NEHALEM_MC8_STATUS 0x00000421\r
-#define MSR_NEHALEM_MC9_STATUS 0x00000425\r
-#define MSR_NEHALEM_MC10_STATUS 0x00000429\r
-#define MSR_NEHALEM_MC11_STATUS 0x0000042D\r
-#define MSR_NEHALEM_MC12_STATUS 0x00000431\r
-#define MSR_NEHALEM_MC13_STATUS 0x00000435\r
-#define MSR_NEHALEM_MC14_STATUS 0x00000439\r
-#define MSR_NEHALEM_MC15_STATUS 0x0000043D\r
-#define MSR_NEHALEM_MC16_STATUS 0x00000441\r
-#define MSR_NEHALEM_MC17_STATUS 0x00000445\r
-#define MSR_NEHALEM_MC18_STATUS 0x00000449\r
-#define MSR_NEHALEM_MC19_STATUS 0x0000044D\r
-#define MSR_NEHALEM_MC20_STATUS 0x00000451\r
-#define MSR_NEHALEM_MC21_STATUS 0x00000455\r
-/// @}\r
-\r
-\r
-/**\r
- Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs."\r
-\r
- The MSR_MC3_ADDR register is either not implemented or contains no address\r
- if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not\r
- implemented in the processor, all reads and writes to this MSR will cause a\r
- general-protection exception.\r
-\r
- The MSR_MC4_ADDR register is either not implemented or contains no address\r
- if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not\r
- implemented in the processor, all reads and writes to this MSR will cause a\r
- general-protection exception.\r
-\r
- @param ECX MSR_NEHALEM_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_NEHALEM_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_NEHALEM_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_NEHALEM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
- MSR_NEHALEM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
- MSR_NEHALEM_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
- MSR_NEHALEM_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
- MSR_NEHALEM_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
- MSR_NEHALEM_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
- MSR_NEHALEM_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
- MSR_NEHALEM_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
- MSR_NEHALEM_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
- MSR_NEHALEM_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
- MSR_NEHALEM_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
- MSR_NEHALEM_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
- MSR_NEHALEM_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
- MSR_NEHALEM_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
- MSR_NEHALEM_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
- MSR_NEHALEM_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
- MSR_NEHALEM_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
- MSR_NEHALEM_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
- MSR_NEHALEM_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
- @{\r
-**/\r
-#define MSR_NEHALEM_MC3_ADDR 0x0000040E\r
-#define MSR_NEHALEM_MC4_ADDR 0x00000412\r
-#define MSR_NEHALEM_MC5_ADDR 0x00000416\r
-#define MSR_NEHALEM_MC6_ADDR 0x0000041A\r
-#define MSR_NEHALEM_MC7_ADDR 0x0000041E\r
-#define MSR_NEHALEM_MC8_ADDR 0x00000422\r
-#define MSR_NEHALEM_MC9_ADDR 0x00000426\r
-#define MSR_NEHALEM_MC10_ADDR 0x0000042A\r
-#define MSR_NEHALEM_MC11_ADDR 0x0000042E\r
-#define MSR_NEHALEM_MC12_ADDR 0x00000432\r
-#define MSR_NEHALEM_MC13_ADDR 0x00000436\r
-#define MSR_NEHALEM_MC14_ADDR 0x0000043A\r
-#define MSR_NEHALEM_MC15_ADDR 0x0000043E\r
-#define MSR_NEHALEM_MC16_ADDR 0x00000442\r
-#define MSR_NEHALEM_MC17_ADDR 0x00000446\r
-#define MSR_NEHALEM_MC18_ADDR 0x0000044A\r
-#define MSR_NEHALEM_MC19_ADDR 0x0000044E\r
-#define MSR_NEHALEM_MC20_ADDR 0x00000452\r
-#define MSR_NEHALEM_MC21_ADDR 0x00000456\r
-/// @}\r
-\r
-\r
/**\r
Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
- branch record registers on the last branch record stack. This part of the\r
- stack contains pointers to the source instruction for one of the last\r
- sixteen branches, exceptions, or interrupts taken by the processor. See\r
- also: - Last Branch Record Stack TOS at 1C9H - Section 17.6.1, "LBR\r
- Stack.".\r
+ branch record registers on the last branch record stack. The From_IP part of\r
+ the stack contains pointers to the source instruction. See also: - Last\r
+ Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in\r
+ Section 17.4.8.1.\r
\r
@param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
@param EAX Lower 32-bits of MSR value.\r
/**\r
Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
record registers on the last branch record stack. This part of the stack\r
- contains pointers to the destination instruction for one of the last sixteen\r
- branches, exceptions, or interrupts taken by the processor.\r
+ contains pointers to the destination instruction.\r
\r
@param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
\r
\r
/**\r
- Package. See Section 18.7.2.1, "Uncore Performance Monitoring Management\r
+ Package. See Section 18.8.2.1, "Uncore Performance Monitoring Management\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
\r
\r
/**\r
- Package. See Section 18.7.2.3, "Uncore Address/Opcode Match MSR.".\r
+ Package. See Section 18.8.2.3, "Uncore Address/Opcode Match MSR.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
@param EAX Lower 32-bits of MSR value.\r
\r
\r
/**\r
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PMCi\r
/// @}\r
\r
/**\r
- Package. See Section 18.7.2.2, "Uncore Performance Event Configuration\r
+ Package. See Section 18.8.2.2, "Uncore Performance Event Configuration\r
Facility.".\r
\r
@param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi\r
projects / mirror_edk2.git / blobdiff