UefiCpuPkg/Msr: Add CPUID signature check MACROs

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / Xeon5600Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index ea22e22be946be433b338d69b61b7f9327d5dff3..ad7128ae952b026db6d5e4bab766119bb3eb8996 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -26,6 +26,23 @@
 \r
 #include <Register/ArchitecturalMsr.h>\r
 \r
+/**\r
+  Is Intel(R) Xeon(R) Processor Series 5600?\r
+\r
+  @param   DisplayFamily  Display Family ID\r
+  @param   DisplayModel   Display Model ID\r
+\r
+  @retval  TRUE   Yes, it is.\r
+  @retval  FALSE  No, it isn't.\r
+**/\r
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
+  (DisplayFamily == 0x06 && \\r
+   (                        \\r
+    DisplayModel == 0x25 || \\r
+    DisplayModel == 0x2C    \\r
+    )                       \\r
+   )\r
+\r
 /**\r
   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
   handler to handle unsuccessful read of this MSR.\r