UefiCpuPkg/Msr: Add CPUID signature check MACROs

[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonE7Msr.h

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index 3128c4b8dd11b5238df079e38b2ce9423cd398cb..d509660c527e7fab7a65546c2eb5c4442e95c96d 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not\r
   provided for that MSR.\r
 \r
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -17,7 +17,7 @@
 \r
   @par Specification Reference:\r
   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
-  December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7.\r
+  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.8.\r
 \r
 **/\r
 \r
@@ -26,6 +26,94 @@
 \r
 #include <Register/ArchitecturalMsr.h>\r
 \r
+/**\r
+  Is Intel(R) Xeon(R) Processor E7 Family?\r
+\r
+  @param   DisplayFamily  Display Family ID\r
+  @param   DisplayModel   Display Model ID\r
+\r
+  @retval  TRUE   Yes, it is.\r
+  @retval  FALSE  No, it isn't.\r
+**/\r
+#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \\r
+  (DisplayFamily == 0x06 && \\r
+   (                        \\r
+    DisplayModel == 0x2F    \\r
+    )                       \\r
+   )\r
+\r
+/**\r
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
+  handler to handle unsuccessful read of this MSR.\r
+\r
+  @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);\r
+  AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);\r
+  @endcode\r
+  @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
+**/\r
+#define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    ///\r
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
+    /// MSR, the configuration of AES instruction set availability is as\r
+    /// follows: 11b: AES instructions are not available until next RESET.\r
+    /// otherwise, AES instructions are available. Note, AES instruction set\r
+    /// is not available if read is unsuccessful. If the configuration is not\r
+    /// 01b, AES instruction can be mis-configured if a privileged agent\r
+    /// unintentionally writes 11b.\r
+    ///\r
+    UINT32  AESConfiguration:2;\r
+    UINT32  Reserved1:30;\r
+    UINT32  Reserved2:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+  Thread. Offcore Response Event Select Register (R/W).\r
+\r
+  @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  UINT64  Msr;\r
+\r
+  Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);\r
+  AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);\r
+  @endcode\r
+  @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
+**/\r
+#define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7\r
+\r
+\r
 /**\r
   Package. Reserved Attempt to read/write will cause #UD.\r
 \r