UefiCpuPkg: Clean up source files

[mirror_edk2.git] / UefiCpuPkg / Library / BaseUefiCpuLib / Ia32 / InitializeFpu.S

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
index 4972bc2e7f3b0394f1bff68577fcf0be25d66acd..0a1a9198f616923fdfecbbddacaad0d117834970 100644 (file)
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.S
@@ -1,6 +1,6 @@
 #------------------------------------------------------------------------------\r
 #*\r
-#*   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
+#*   Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
 #*   This program and the accompanying materials\r
 #*   are licensed and made available under the terms and conditions of the BSD License\r
 #*   which accompanies this distribution.  The full text of the license may be found at\r
@@ -13,7 +13,7 @@
 #------------------------------------------------------------------------------\r
 \r
 #\r
-# Float control word initial value: \r
+# Float control word initial value:\r
 # all exceptions masked, double-precision, round-to-nearest\r
 #\r
 ASM_PFX(mFpuControlWord): .word     0x027F\r
@@ -41,7 +41,7 @@ ASM_PFX(InitializeFloatingPointUnits):
     #\r
     finit\r
     fldcw   ASM_PFX(mFpuControlWord)\r
-    \r
+\r
     #\r
     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test\r
     # whether the processor supports SSE instruction.\r
@@ -50,14 +50,14 @@ ASM_PFX(InitializeFloatingPointUnits):
     cpuid\r
     btl     $25, %edx\r
     jnc     Done\r
-    \r
+\r
     #\r
     # Set OSFXSR bit 9 in CR4\r
     #\r
-    movl    %cr4, %eax \r
+    movl    %cr4, %eax\r
     or      $0x200, %eax\r
     movl    %eax, %cr4\r
-    \r
+\r
     #\r
     # The processor should support SSE instruction and we can use\r
     # ldmxcsr instruction\r