UefiCpuPkg/LocalApicLib: Add GetProcessorLocation2ByApicId() API

[mirror_edk2.git] / UefiCpuPkg / Library / BaseXApicLib / BaseXApicLib.c

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 7d66d89dfda8953884404b31a09d693a129241c8..fd8c494a9f26beacbc63e874b656c52ab6837612 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r

-  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r

   Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r


@@ -1156,3 +1156,126 @@ GetProcessorLocationByApicId (
     *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
   }\r
 }\r
     *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
   }\r
 }\r

+\r
+/**\r
+  Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.\r
+\r
+  The algorithm assumes the target system has symmetry across physical\r
+  package boundaries with respect to the number of threads per core, number of\r
+  cores per module, number of modules per tile, number of tiles per die, number\r
+  of dies per package.\r
+\r
+  @param[in]   InitialApicId Initial APIC ID of the target logical processor.\r
+  @param[out]  Package       Returns the processor package ID.\r
+  @param[out]  Die           Returns the processor die ID.\r
+  @param[out]  Tile          Returns the processor tile ID.\r
+  @param[out]  Module        Returns the processor module ID.\r
+  @param[out]  Core          Returns the processor core ID.\r
+  @param[out]  Thread        Returns the processor thread ID.\r
+**/\r
+VOID\r
+EFIAPI\r
+GetProcessorLocation2ByApicId (\r
+  IN  UINT32  InitialApicId,\r
+  OUT UINT32  *Package  OPTIONAL,\r
+  OUT UINT32  *Die      OPTIONAL,\r
+  OUT UINT32  *Tile     OPTIONAL,\r
+  OUT UINT32  *Module   OPTIONAL,\r
+  OUT UINT32  *Core     OPTIONAL,\r
+  OUT UINT32  *Thread   OPTIONAL\r
+  )\r
+{\r
+  CPUID_EXTENDED_TOPOLOGY_EAX         ExtendedTopologyEax;\r
+  CPUID_EXTENDED_TOPOLOGY_ECX         ExtendedTopologyEcx;\r
+  UINT32                              MaxStandardCpuIdIndex;\r
+  UINT32                              Index;\r
+  UINTN                               LevelType;\r
+  UINT32                              Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+  UINT32                              *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+\r
+  for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
+    Bits[LevelType] = 0;\r
+  }\r
+\r
+  //\r
+  // Get max index of CPUID\r
+  //\r
+  AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);\r
+  if (MaxStandardCpuIdIndex < CPUID_V2_EXTENDED_TOPOLOGY) {\r
+    if (Die != NULL) {\r
+      *Die = 0;\r
+    }\r
+    if (Tile != NULL) {\r
+      *Tile = 0;\r
+    }\r
+    if (Module != NULL) {\r
+      *Module = 0;\r
+    }\r
+    GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r
+    return;\r
+  }\r
+\r
+  //\r
+  // If the V2 extended topology enumeration leaf is available, it\r
+  // is the preferred mechanism for enumerating topology.\r
+  //\r
+  for (Index = 0; ; Index++) {\r
+    AsmCpuidEx(\r
+      CPUID_V2_EXTENDED_TOPOLOGY,\r
+      Index,\r
+      &ExtendedTopologyEax.Uint32,\r
+      NULL,\r
+      &ExtendedTopologyEcx.Uint32,\r
+      NULL\r
+      );\r
+\r
+    LevelType = ExtendedTopologyEcx.Bits.LevelType;\r
+\r
+    //\r
+    // first level reported should be SMT.\r
+    //\r
+    ASSERT ((Index != 0) || (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT));\r
+    if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
+      break;\r
+    }\r
+    ASSERT (LevelType < ARRAY_SIZE (Bits));\r
+    Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r
+  }\r
+\r
+  for (LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
+    //\r
+    // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored\r
+    // and treated as an extension of the last known level (i.e., level-1 in this case).\r
+    //\r
+    if (Bits[LevelType] == 0) {\r
+      Bits[LevelType] = Bits[LevelType - 1];\r
+    }\r
+  }\r
+\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE    ] = Die;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE   ] = Tile;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE   ]    = Core;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT    ]    = Thread;\r
+\r
+  Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r
+\r
+  for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r
+      ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
+      ; LevelType ++\r
+      ) {\r
+    if (Location[LevelType] != NULL) {\r
+      //\r
+      // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r
+      // topology ID of the next level type.\r
+      //\r
+      *Location[LevelType] = InitialApicId >> Bits[LevelType - 1];\r
+\r
+      //\r
+      // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.\r
+      //\r
+      *Location[LevelType] &= (1 << (Bits[LevelType] - Bits[LevelType - 1])) - 1;\r
+    }\r
+  }\r
+}\r