Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
if (FamilyId == 0x04 || FamilyId == 0x05) {\r
//\r
AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
if (FamilyId == 0x04 || FamilyId == 0x05) {\r
//\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
}\r
\r
@param IcrLow 32-bit value to be written to the low half of ICR.\r
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
\r
@param IcrLow 32-bit value to be written to the low half of ICR.\r
@param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r
//\r
if (LocalApicBaseAddressMsrSupported ()) {\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
//\r
if (LocalApicBaseAddressMsrSupported ()) {\r
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r
\r
In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r
- In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r
+ In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
the 32-bit local APIC ID is returned as initial APIC ID.\r
\r
@return 32-bit initial local APIC ID of the executing processor.\r
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
\r
//\r
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
\r
//\r
// And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
// And CPUID.0BH:EBX[15:0] reports a non-zero value,\r
// Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r
// Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r
if ((ApicId = GetInitialApicId ()) < 0x100) {\r
//\r
// If the initial local APIC ID is less 0x100, read APIC ID from\r
if ((ApicId = GetInitialApicId ()) < 0x100) {\r
//\r
// If the initial local APIC ID is less 0x100, read APIC ID from\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
\r
@param ApicId The local APIC ID of the target processor.\r
@param Vector The vector number of the interrupt being sent.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
\r
if StartupRoutine >= 1M, then ASSERT.\r
if StartupRoutine is not multiple of 4K, then ASSERT.\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
@return 32-bit address used to send an MSI to the Local APIC.\r
**/\r
UINT32\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
Interrupt (MSI) to the Local APIC of the currently executing processor.\r
\r
If Vector is not in range 0x10..0xFE, then ASSERT().\r
If DeliveryMode is not supported, then ASSERT().\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
is handled. The only supported values are:\r
0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
4: LOCAL_APIC_DELIVERY_MODE_NMI\r
5: LOCAL_APIC_DELIVERY_MODE_INIT\r
7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
FALSE specifies an edge triggered interrupt.\r
@param AssertionLevel Ignored if LevelTriggered is FALSE.\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
when the interrupt line is deasserted.\r
\r
@return 64-bit data value used to send an MSI to the Local APIC.\r
**/\r
UINT64\r
\r
ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
\r
ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r