This local APIC library instance supports x2APIC capable processors\r
which have xAPIC and x2APIC modes.\r
\r
- Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+ Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
#include <Library/LocalApicLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/TimerLib.h>\r
-#include <Library/PcdLib.h>\r
\r
//\r
// Library internal functions\r
//\r
\r
+/**\r
+ Retrieve the base address of local APIC.\r
+\r
+ @return The base address of local APIC.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+GetLocalApicBaseAddress (\r
+ VOID\r
+ )\r
+{\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+ \r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+ \r
+ return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r
+ (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r
+}\r
+\r
+/**\r
+ Set the base address of local APIC.\r
+\r
+ If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r
+\r
+ @param[in] BaseAddress Local APIC base address to be set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLocalApicBaseAddress (\r
+ IN UINTN BaseAddress\r
+ )\r
+{\r
+ MSR_IA32_APIC_BASE ApicBaseMsr;\r
+\r
+ ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
+\r
+ ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r
+\r
+ ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r
+ ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+\r
+ AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r
+}\r
+\r
/**\r
Read from a local APIC register.\r
\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- return MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset);\r
+ return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
ASSERT ((MmioOffset & 0xf) == 0);\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + MmioOffset, Value);\r
+ MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
} else {\r
//\r
// DFR is not supported in x2APIC mode.\r
{\r
UINT64 MsrValue;\r
LOCAL_APIC_ICR_LOW IcrLowReg;\r
+ UINTN LocalApciBaseAddress;\r
\r
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
ASSERT (ApicId <= 0xff);\r
//\r
// For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r
//\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
- MmioWrite32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
+ LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r
+ MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET, IcrLow);\r
do {\r
- IcrLowReg.Uint32 = MmioRead32 (PcdGet32 (PcdCpuLocalApicBaseAddress) + XAPIC_ICR_LOW_OFFSET);\r
+ IcrLowReg.Uint32 = MmioRead32 (LocalApciBaseAddress + XAPIC_ICR_LOW_OFFSET);\r
} while (IcrLowReg.Bits.DeliveryStatus != 0);\r
} else {\r
//\r
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an \r
// interrupt in x2APIC mode.\r
//\r
- MsrValue = (((UINT64)ApicId) << 32) | IcrLow;\r
+ MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
}\r
}\r
WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
}\r
\r
+/**\r
+ Get the 32-bit address that a device should use to send a Message Signaled \r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI \r
+GetApicMsiAddress (\r
+ VOID\r
+ )\r
+{\r
+ LOCAL_APIC_MSI_ADDRESS MsiAddress;\r
+\r
+ //\r
+ // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+ // of the currently executing processor.\r
+ //\r
+ MsiAddress.Uint32 = 0;\r
+ MsiAddress.Bits.BaseAddress = 0xFEE;\r
+ MsiAddress.Bits.DestinationId = GetApicId ();\r
+ return MsiAddress.Uint32;\r
+}\r
+ \r
+/**\r
+ Get the 64-bit data value that a device should use to send a Message Signaled \r
+ Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+ If Vector is not in range 0x10..0xFE, then ASSERT().\r
+ If DeliveryMode is not supported, then ASSERT().\r
+ \r
+ @param Vector The 8-bit interrupt vector associated with the MSI. \r
+ Must be in the range 0x10..0xFE\r
+ @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r
+ is handled. The only supported values are:\r
+ 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+ 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+ 2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+ 4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+ 5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+ 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+ \r
+ @param LevelTriggered TRUE specifies a level triggered interrupt. \r
+ FALSE specifies an edge triggered interrupt.\r
+ @param AssertionLevel Ignored if LevelTriggered is FALSE.\r
+ TRUE specifies a level triggered interrupt that active \r
+ when the interrupt line is asserted.\r
+ FALSE specifies a level triggered interrupt that active \r
+ when the interrupt line is deasserted.\r
+\r
+ @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI \r
+GetApicMsiValue (\r
+ IN UINT8 Vector,\r
+ IN UINTN DeliveryMode,\r
+ IN BOOLEAN LevelTriggered,\r
+ IN BOOLEAN AssertionLevel\r
+ )\r
+{\r
+ LOCAL_APIC_MSI_DATA MsiData;\r
+\r
+ ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
+ ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
+ \r
+ MsiData.Uint64 = 0;\r
+ MsiData.Bits.Vector = Vector;\r
+ MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
+ if (LevelTriggered) {\r
+ MsiData.Bits.TriggerMode = 1;\r
+ if (AssertionLevel) {\r
+ MsiData.Bits.Level = 1;\r
+ }\r
+ }\r
+ return MsiData.Uint64;\r
+}\r
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