UefiCpuPkg CpuCommFeaturesLib: Disable TraceEn at the beginning

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / LimitCpuIdMaxval.c

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
index 3d41efe9e993804a2e05d2fe6fe7f9635999718e..906ed6540839c9287f58b30db01bb87f001ce3db 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
@@ -2,13 +2,7 @@
   LimitCpuidMaxval Feature.\r
 \r
   Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -70,6 +64,20 @@ LimitCpuidMaxvalInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
+  //\r
+  // The scope of LimitCpuidMaxval bit in the MSR_IA32_MISC_ENABLE is core for below\r
+  // processor type, only program MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r
     ProcessorNumber,\r
     Msr,\r