UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.

[mirror_edk2.git] / UefiCpuPkg / Library / CpuCommonFeaturesLib / MachineCheck.c

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index c4eca062fdcdecda72235e9035ff4805c6161c2e..f8bee53819f476bb2bcc41db2d4bcf26693674f8 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -140,6 +140,32 @@ McaInitialize (
   MSR_IA32_MCG_CAP_REGISTER  McgCap;\r
   UINT32                     BankIndex;\r
 \r
+  //\r
+  // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is core for below processor type, only program\r
+  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 in each core.\r
+  //\r
+  if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
+  //\r
+  // The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program\r
+  // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.\r
+  //\r
+  if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   if (State) {\r
     McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
     for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r
@@ -301,6 +327,18 @@ LmceInitialize (
 {\r
   MSR_IA32_FEATURE_CONTROL_REGISTER    *MsrRegister;\r
 \r
+  //\r
+  // The scope of FastStrings bit in the MSR_IA32_MISC_ENABLE is core for below processor type, only program \r
+  // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r
+  //\r
+  if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+    if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
+      return RETURN_SUCCESS;\r
+    }\r
+  }\r
+\r
   ASSERT (ConfigData != NULL);\r
   MsrRegister = (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData;\r
   if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {\r