SystemContext.SystemContextX64->ExceptionData = ReservedVectors[ExceptionType].ExceptionData;\r
}\r
\r
+/**\r
+ Setup separate stack for given exceptions.\r
+\r
+ @param[in] StackSwitchData Pointer to data required for setuping up\r
+ stack switch.\r
+\r
+ @retval EFI_SUCCESS The exceptions have been successfully\r
+ initialized with new stack.\r
+ @retval EFI_INVALID_PARAMETER StackSwitchData contains invalid content.\r
+\r
+**/\r
+EFI_STATUS\r
+ArchSetupExcpetionStack (\r
+ IN CPU_EXCEPTION_INIT_DATA *StackSwitchData\r
+ )\r
+{\r
+ IA32_DESCRIPTOR Gdtr;\r
+ IA32_DESCRIPTOR Idtr;\r
+ IA32_IDT_GATE_DESCRIPTOR *IdtTable;\r
+ IA32_TSS_DESCRIPTOR *TssDesc;\r
+ IA32_TASK_STATE_SEGMENT *Tss;\r
+ UINTN StackTop;\r
+ UINTN Index;\r
+ UINTN Vector;\r
+ UINTN TssBase;\r
+ UINTN GdtSize;\r
+\r
+ if (StackSwitchData == NULL ||\r
+ StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||\r
+ StackSwitchData->X64.KnownGoodStackTop == 0 ||\r
+ StackSwitchData->X64.KnownGoodStackSize == 0 ||\r
+ StackSwitchData->X64.StackSwitchExceptions == NULL ||\r
+ StackSwitchData->X64.StackSwitchExceptionNumber == 0 ||\r
+ StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||\r
+ StackSwitchData->X64.GdtTable == NULL ||\r
+ StackSwitchData->X64.IdtTable == NULL ||\r
+ StackSwitchData->X64.ExceptionTssDesc == NULL ||\r
+ StackSwitchData->X64.ExceptionTss == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // The caller is responsible for that the GDT table, no matter the existing\r
+ // one or newly allocated, has enough space to hold descriptors for exception\r
+ // task-state segments.\r
+ //\r
+ if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >\r
+ ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // One task gate descriptor and one task-state segment are needed.\r
+ //\r
+ if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Interrupt stack table supports only 7 vectors.\r
+ //\r
+ TssDesc = StackSwitchData->X64.ExceptionTssDesc;\r
+ Tss = StackSwitchData->X64.ExceptionTss;\r
+ if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Initialize new GDT table and/or IDT table, if any\r
+ //\r
+ AsmReadIdtr (&Idtr);\r
+ AsmReadGdtr (&Gdtr);\r
+\r
+ GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) -\r
+ (UINTN)(StackSwitchData->X64.GdtTable);\r
+ if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {\r
+ CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+ Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;\r
+ Gdtr.Limit = (UINT16)GdtSize - 1;\r
+ }\r
+\r
+ if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {\r
+ Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;\r
+ }\r
+ if (StackSwitchData->X64.IdtTableSize > 0) {\r
+ Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);\r
+ }\r
+\r
+ //\r
+ // Fixup current task descriptor. Task-state segment for current task will\r
+ // be filled by processor during task switching.\r
+ //\r
+ TssBase = (UINTN)Tss;\r
+\r
+ TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
+ TssDesc->Bits.BaseLow = (UINT16)TssBase;\r
+ TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);\r
+ TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;\r
+ TssDesc->Bits.P = 1;\r
+ TssDesc->Bits.LimitHigh = 0;\r
+ TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);\r
+ TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);\r
+\r
+ //\r
+ // Fixup exception task descriptor and task-state segment\r
+ //\r
+ StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT;\r
+ StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);\r
+ IdtTable = StackSwitchData->X64.IdtTable;\r
+ for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) {\r
+ //\r
+ // Fixup IST\r
+ //\r
+ Tss->IST[Index] = StackTop;\r
+ StackTop -= StackSwitchData->X64.KnownGoodStackSize;\r
+\r
+ //\r
+ // Set the IST field to enable corresponding IST\r
+ //\r
+ Vector = StackSwitchData->X64.StackSwitchExceptions[Index];\r
+ if (Vector >= CPU_EXCEPTION_NUM ||\r
+ Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {\r
+ continue;\r
+ }\r
+ IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);\r
+ }\r
+\r
+ //\r
+ // Publish GDT\r
+ //\r
+ AsmWriteGdtr (&Gdtr);\r
+\r
+ //\r
+ // Load current task\r
+ //\r
+ AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base));\r
+\r
+ //\r
+ // Publish IDT\r
+ //\r
+ AsmWriteIdtr (&Idtr);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
/**\r
Display CPU information.\r
\r
projects / mirror_edk2.git / blobdiff