UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain

[mirror_edk2.git] / UefiCpuPkg / Library / SmmCpuFeaturesLib / X64 / SmiEntry.nasm

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
index c801591fc7642044e0459ee27b51b9b2e80bc10c..90a9fd489b40dd5654d8f39ec869f04db4dbaf1d 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -61,6 +61,11 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
 global ASM_PFX(gcStmSmiHandlerSize)\r
 global ASM_PFX(gcStmSmiHandlerOffset)\r
 \r
+ASM_PFX(gStmSmbase)      EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmSmiStack)    EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmiCr3)      EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
     DEFAULT REL\r
     SECTION .text\r
 \r
@@ -76,8 +81,8 @@ _StmSmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov     edi, strict dword 0\r
+StmSmbasePatch:\r
     lea     eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -97,14 +102,14 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+    mov     esp, strict dword 0\r
+StmSmiStackPatch:\r
     jmp     ProtFlatMode\r
 \r
 BITS 64\r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, offset gStmSmiCr3\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+    mov     eax, strict dword 0\r
+StmSmiCr3Patch:\r
     mov     cr3, rax\r
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r
@@ -119,8 +124,8 @@ ASM_PFX(gStmSmiCr3): DD 0
     ltr     ax\r
 \r
 ; enable NXE if supported\r
-    DB      0xb0                        ; mov al, imm8\r
-ASM_PFX(gStmXdSupported):     DB      1\r
+    mov al, strict byte 1\r
+StmXdSupportedPatch:\r
     cmp     al, 0\r
     jz      @SkipXd\r
 ;\r
@@ -159,7 +164,8 @@ Base:
     mov     cr0, rbx\r
     retf\r
 @LongMode:                              ; long mode (64-bit code) starts here\r
-    mov     rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+    mov     rax, strict qword 0         ;  mov     rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+StmSmiEntrySmiHandlerIdtrAbsAddr:\r
     lidt    [rax]\r
     lea     ebx, [rdi + DSC_OFFSET]\r
     mov     ax, [rbx + DSC_DS]\r
@@ -170,7 +176,9 @@ Base:
     mov     gs, eax\r
     mov     ax, [rbx + DSC_SS]\r
     mov     ss, eax\r
-\r
+    mov     rax, strict qword 0           ;   mov     rax, CommonHandler\r
+StmSmiEntryCommonHandlerAbsAddr:\r
+    jmp     rax\r
 CommonHandler:\r
     mov     rbx, [rsp + 0x08]             ; rbx <- CpuIndex\r
 \r
@@ -178,34 +186,29 @@ CommonHandler:
     ; Save FP registers\r
     ;\r
     sub     rsp, 0x200\r
-    DB      0x48                         ; FXSAVE64\r
-    fxsave  [rsp]\r
+    fxsave64 [rsp]\r
 \r
     add     rsp, -0x20\r
 \r
     mov     rcx, rbx\r
-    mov     rax, CpuSmmDebugEntry\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugEntry)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, SmiRendezvous          ; rax <- absolute addr of SmiRedezvous\r
-    call    rax\r
+    call    ASM_PFX(SmiRendezvous)\r
 \r
     mov     rcx, rbx\r
-    mov     rax, CpuSmmDebugExit\r
-    call    rax\r
+    call    ASM_PFX(CpuSmmDebugExit)\r
 \r
     add     rsp, 0x20\r
 \r
     ;\r
     ; Restore FP registers\r
     ;\r
-    DB      0x48                         ; FXRSTOR64\r
-    fxrstor [rsp]\r
+    fxrstor64 [rsp]\r
 \r
     add     rsp, 0x200\r
 \r
-    mov     rax, ASM_PFX(gStmXdSupported)\r
+    lea     rax, [ASM_PFX(gStmXdSupported)]\r
     mov     al, [rax]\r
     cmp     al, 0\r
     jz      .1\r
@@ -225,7 +228,7 @@ _StmSmiHandler:
 ; Check XD disable bit\r
 ;\r
     xor     r8, r8\r
-    mov     rax, ASM_PFX(gStmXdSupported)\r
+    lea     rax, [ASM_PFX(gStmXdSupported)]\r
     mov     al, [rax]\r
     cmp     al, 0\r
     jz      @StmXdDone\r
@@ -246,8 +249,8 @@ _StmSmiHandler:
 \r
     ; below step is needed, because STM does not run above code.\r
     ; we have to run below code to set IDT/CR0/CR4\r
-\r
-    mov     rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+    mov     rax, strict qword 0        ;  mov     rax, ASM_PFX(gStmSmiHandlerIdtr)\r
+StmSmiHandlerIdtrAbsAddr:\r
     lidt    [rax]\r
 \r
     mov     rax, cr0\r
@@ -261,3 +264,16 @@ _StmSmiHandler:
 \r
 ASM_PFX(gcStmSmiHandlerSize)   : DW      $ - _StmSmiEntryPoint\r
 ASM_PFX(gcStmSmiHandlerOffset) : DW      _StmSmiHandler - _StmSmiEntryPoint\r
+\r
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)\r
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):\r
+    lea    rax, [ASM_PFX(gStmSmiHandlerIdtr)]\r
+    lea    rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+    lea    rcx, [StmSmiHandlerIdtrAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+\r
+    lea    rax, [CommonHandler]\r
+    lea    rcx, [StmSmiEntryCommonHandlerAbsAddr]\r
+    mov    qword [rcx - 8], rax\r
+    ret\r