UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmbase" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 94e5ab2c0ee22398fb846ac720ada8a3535be9e4..554629536a5db5da465f24397289b30dd1a346b6 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
 /** @file\r
 Code for Processor S3 restoration\r
 \r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
+#pragma pack(1)\r
 typedef struct {\r
   UINTN             Lock;\r
   VOID              *StackStart;\r
@@ -23,7 +24,9 @@ typedef struct {
   IA32_DESCRIPTOR   IdtrProfile;\r
   UINT32            BufferStart;\r
   UINT32            Cr3;\r
+  UINTN             InitializeFloatingPointUnitsAddress;\r
 } MP_CPU_EXCHANGE_INFO;\r
+#pragma pack()\r
 \r
 typedef struct {\r
   UINT8 *RendezvousFunnelAddress;\r
@@ -456,6 +459,7 @@ PrepareApStartupVector (
   mExchangeInfo->StackSize   = mAcpiCpuData.StackSize;\r
   mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
   mExchangeInfo->Cr3         = (UINT32) (AsmReadCr3 ());\r
+  mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
 }\r
 \r
 /**\r