PeCoffGetEntryPointLib: Fix spelling issue

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / CpuS3.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 532b7c44bd17a5b0213f68f90eeec11496521e5a..940450149810d3dbebea356f8eab31d5ceb8422e 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
 /** @file\r
 Code for Processor S3 restoration\r
 \r
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -315,7 +315,7 @@ SetProcessorRegister (
     case MemoryMapped:\r
       AcquireSpinLock (mMemoryMappedLock);\r
       MmioBitFieldWrite32 (\r
-        RegisterTableEntry->Index,\r
+        (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
         RegisterTableEntry->ValidBitStart,\r
         RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
         (UINT32)RegisterTableEntry->Value\r
@@ -826,19 +826,23 @@ CopyRegisterTable (
 \r
   CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
   for (Index = 0; Index < NumberOfCpus; Index++) {\r
-    DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);\r
-    ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);\r
-    CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);\r
-    //\r
-    // Go though all MSRs in register table to initialize MSR spin lock\r
-    //\r
-    RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;\r
-    for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
-      if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
-        //\r
-        // Initialize MSR spin lock only for those MSRs need bit field writing\r
-        //\r
-        InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
+    if (DestinationRegisterTableList[Index].AllocatedSize != 0) {\r
+      RegisterTableEntry = AllocateCopyPool (\r
+        DestinationRegisterTableList[Index].AllocatedSize,\r
+        (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry\r
+        );\r
+      ASSERT (RegisterTableEntry != NULL);\r
+      DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;\r
+      //\r
+      // Go though all MSRs in register table to initialize MSR spin lock\r
+      //\r
+      for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {\r
+        if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {\r
+          //\r
+          // Initialize MSR spin lock only for those MSRs need bit field writing\r
+          //\r
+          InitMsrSpinLockByIndex (RegisterTableEntry->Index);\r
+        }\r
       }\r
     }\r
   }\r