**/\r
VOID\r
GetPageTable (\r
- OUT UINTN *Base,\r
- OUT BOOLEAN *FiveLevels OPTIONAL\r
+ OUT UINTN *Base,\r
+ OUT BOOLEAN *FiveLevels OPTIONAL\r
)\r
{\r
*Base = ((mInternalCr3 == 0) ?\r
- (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :\r
- mInternalCr3);\r
+ (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :\r
+ mInternalCr3);\r
if (FiveLevels != NULL) {\r
*FiveLevels = FALSE;\r
}\r
VOID\r
)\r
{\r
- UINTN PageFaultHandlerHookAddress;\r
- IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
- EFI_STATUS Status;\r
+ UINTN PageFaultHandlerHookAddress;\r
+ IA32_IDT_GATE_DESCRIPTOR *IdtEntry;\r
+ EFI_STATUS Status;\r
\r
//\r
// Initialize spin lock\r
\r
if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||\r
HEAP_GUARD_NONSTOP_MODE ||\r
- NULL_DETECTION_NONSTOP_MODE) {\r
+ NULL_DETECTION_NONSTOP_MODE)\r
+ {\r
//\r
// Set own Page Fault entry instead of the default one, because SMM Profile\r
// feature depends on IRET instruction to do Single Step\r
//\r
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;\r
- IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;\r
- IdtEntry += EXCEPT_IA32_PAGE_FAULT;\r
- IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;\r
- IdtEntry->Bits.Reserved_0 = 0;\r
- IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
- IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
+ IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+ IdtEntry += EXCEPT_IA32_PAGE_FAULT;\r
+ IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;\r
+ IdtEntry->Bits.Reserved_0 = 0;\r
+ IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
+ IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
} else {\r
//\r
// Register SMM Page Fault Handler\r
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
InitializeIDTSmmStackGuard ();\r
}\r
+\r
return Gen4GPageTable (TRUE);\r
}\r
\r
VOID\r
EFIAPI\r
SmiPFHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
)\r
{\r
- UINTN PFAddress;\r
- UINTN GuardPageAddress;\r
- UINTN CpuIndex;\r
+ UINTN PFAddress;\r
+ UINTN GuardPageAddress;\r
+ UINTN CpuIndex;\r
\r
ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);\r
\r
// or SMM page protection violation.\r
//\r
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&\r
- (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {\r
+ (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))\r
+ {\r
DumpCpuContext (InterruptType, SystemContext);\r
- CpuIndex = GetCpuIndex ();\r
+ CpuIndex = GetCpuIndex ();\r
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);\r
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
(PFAddress >= GuardPageAddress) &&\r
- (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {\r
+ (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))\r
+ {\r
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));\r
} else {\r
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);\r
- );\r
+ );\r
} else {\r
DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
- );\r
+ );\r
}\r
\r
if (HEAP_GUARD_NONSTOP_MODE) {\r
goto Exit;\r
}\r
}\r
+\r
CpuDeadLoop ();\r
goto Exit;\r
}\r
// If a page fault occurs in non-SMRAM range.\r
//\r
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||\r
- (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
+ (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))\r
+ {\r
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
DumpCpuContext (InterruptType, SystemContext);\r
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);\r
- );\r
+ );\r
CpuDeadLoop ();\r
goto Exit;\r
}\r
//\r
// If NULL pointer was just accessed\r
//\r
- if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&\r
- (PFAddress < EFI_PAGE_SIZE)) {\r
+ if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&\r
+ (PFAddress < EFI_PAGE_SIZE))\r
+ {\r
DumpCpuContext (InterruptType, SystemContext);\r
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));\r
DEBUG_CODE (\r
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
- );\r
+ );\r
\r
if (NULL_DETECTION_NONSTOP_MODE) {\r
GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);\r
DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));\r
DEBUG_CODE (\r
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
- );\r
+ );\r
CpuDeadLoop ();\r
goto Exit;\r
}\r
VOID\r
)\r
{\r
- UINTN Index2;\r
- UINTN Index3;\r
- UINT64 *L1PageTable;\r
- UINT64 *L2PageTable;\r
- UINT64 *L3PageTable;\r
- UINTN PageTableBase;\r
- BOOLEAN IsSplitted;\r
- BOOLEAN PageTableSplitted;\r
- BOOLEAN CetEnabled;\r
+ UINTN Index2;\r
+ UINTN Index3;\r
+ UINT64 *L1PageTable;\r
+ UINT64 *L2PageTable;\r
+ UINT64 *L3PageTable;\r
+ UINTN PageTableBase;\r
+ BOOLEAN IsSplitted;\r
+ BOOLEAN PageTableSplitted;\r
+ BOOLEAN CetEnabled;\r
\r
//\r
// Don't mark page table to read-only if heap guard is enabled.\r
//\r
if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {\r
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));\r
- return ;\r
+ return;\r
}\r
\r
//\r
//\r
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));\r
- return ;\r
+ return;\r
}\r
\r
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));\r
// Disable write protection, because we need mark page table to be write protected.\r
// We need *write* page table memory, to mark itself to be *read only*.\r
//\r
- CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
+ CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
if (CetEnabled) {\r
//\r
// CET must be disabled if WP is disabled.\r
//\r
- DisableCet();\r
+ DisableCet ();\r
}\r
- AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);\r
+\r
+ AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);\r
\r
do {\r
DEBUG ((DEBUG_INFO, "Start...\n"));\r
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
PageTableSplitted = (PageTableSplitted || IsSplitted);\r
\r
- for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {\r
+ for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {\r
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r
// 2M\r
continue;\r
}\r
+\r
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
if (L1PageTable == NULL) {\r
continue;\r
}\r
+\r
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
PageTableSplitted = (PageTableSplitted || IsSplitted);\r
}\r
//\r
// Enable write protection, after page table updated.\r
//\r
- AsmWriteCr0 (AsmReadCr0() | CR0_WP);\r
+ AsmWriteCr0 (AsmReadCr0 () | CR0_WP);\r
if (CetEnabled) {\r
//\r
// re-enable CET.\r
//\r
- EnableCet();\r
+ EnableCet ();\r
}\r
\r
- return ;\r
+ return;\r
}\r
\r
/**\r
OUT UINTN *Cr2\r
)\r
{\r
- return ;\r
+ return;\r
}\r
\r
/**\r
IN UINTN Cr2\r
)\r
{\r
- return ;\r
+ return;\r
}\r
\r
/**\r
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