;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
; This program and the accompanying materials\r
; are licensed and made available under the terms and conditions of the BSD License\r
; which accompanies this distribution. The full text of the license may be found at\r
%define MSR_EFER 0xc0000080\r
%define MSR_EFER_XD 0x800\r
\r
+;\r
+; Constants relating to PROCESSOR_SMM_DESCRIPTOR\r
+;\r
%define DSC_OFFSET 0xfb00\r
%define DSC_GDTPTR 0x30\r
%define DSC_GDTSIZ 0x38\r
\r
global ASM_PFX(gcSmiHandlerTemplate)\r
global ASM_PFX(gcSmiHandlerSize)\r
-global ASM_PFX(gSmiCr3)\r
-global ASM_PFX(gSmiStack)\r
-global ASM_PFX(gSmbase)\r
-global ASM_PFX(mXdSupported)\r
+global ASM_PFX(gPatchSmiCr3)\r
+global ASM_PFX(gPatchSmiStack)\r
+global ASM_PFX(gPatchSmbase)\r
+extern ASM_PFX(mXdSupported)\r
+global ASM_PFX(gPatchXdSupported)\r
extern ASM_PFX(gSmiHandlerIdtr)\r
\r
SECTION .text\r
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]\r
mov ax, PROTECT_MODE_CS\r
mov [cs:bx-0x2],ax\r
- DB 0x66, 0xbf ; mov edi, SMBASE\r
-ASM_PFX(gSmbase): DD 0\r
+ mov edi, strict dword 0 ; source operand will be patched\r
+ASM_PFX(gPatchSmbase):\r
lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]\r
mov [cs:bx-0x6],eax\r
mov ebx, cr0\r
o16 mov fs, ax\r
o16 mov gs, ax\r
o16 mov ss, ax\r
- DB 0xbc ; mov esp, imm32\r
-ASM_PFX(gSmiStack): DD 0\r
+ mov esp, strict dword 0 ; source operand will be patched\r
+ASM_PFX(gPatchSmiStack):\r
mov eax, ASM_PFX(gSmiHandlerIdtr)\r
lidt [eax]\r
jmp ProtFlatMode\r
\r
ProtFlatMode:\r
- DB 0xb8 ; mov eax, imm32\r
-ASM_PFX(gSmiCr3): DD 0\r
+ mov eax, strict dword 0 ; source operand will be patched\r
+ASM_PFX(gPatchSmiCr3):\r
mov cr3, eax\r
;\r
; Need to test for CR4 specific bit support\r
.6:\r
\r
; enable NXE if supported\r
- DB 0b0h ; mov al, imm8\r
-ASM_PFX(mXdSupported): DB 1\r
+ mov al, strict byte 1 ; source operand may be patched\r
+ASM_PFX(gPatchXdSupported):\r
cmp al, 0\r
jz @SkipXd\r
;\r
\r
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint\r
\r
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)\r
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):\r
+ ret\r