+\r
+ cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0\r
+ jz .6\r
+; Load TSS\r
+ mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag\r
+ mov eax, TSS_SEGMENT\r
+ ltr ax\r
+.6:\r
+\r
+; enable NXE if supported\r
+ DB 0b0h ; mov al, imm8\r
+ASM_PFX(mXdSupported): DB 1\r
+ cmp al, 0\r
+ jz @SkipXd\r
+;\r
+; Check XD disable bit\r
+;\r
+ mov ecx, MSR_IA32_MISC_ENABLE\r
+ rdmsr\r
+ push edx ; save MSR_IA32_MISC_ENABLE[63-32]\r
+ test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]\r
+ jz .5\r
+ and dx, 0xFFFB ; clear XD Disable bit if it is set\r
+ wrmsr\r
+.5:\r
+ mov ecx, MSR_EFER\r
+ rdmsr\r
+ or ax, MSR_EFER_XD ; enable NXE\r
+ wrmsr\r
+ jmp @XdDone\r
+@SkipXd:\r
+ sub esp, 4\r
+@XdDone:\r
+\r