UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain
authorLiming Gao <liming.gao@intel.com>
Thu, 11 Jan 2018 09:05:15 +0000 (17:05 +0800)
committerLiming Gao <liming.gao@intel.com>
Tue, 16 Jan 2018 15:43:08 +0000 (23:43 +0800)
commite21e355e2ca7fefb15b4df7078f995d3fb9c2b89
treeec7a89e8a5550398b592234626609f155d96fd7d
parent1c7a65eba749ff62e5ba425c5e40e23cfd1de245
UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain

https://bugzilla.tianocore.org/show_bug.cgi?id=849

In V2, use "mov rax, strict qword 0" to replace the hard code db.

1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm