UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / Ia32 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index c2295e48e2ee4cdf2bf0304def2e6bfc541e455f..f7bb9b9a82e52f216f8e1e21cdd5f991b449eba8 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)\r
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
-global ASM_PFX(gSmmCr3)\r
+global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gSmmCr4)\r
 global ASM_PFX(gSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
@@ -41,23 +41,35 @@ ASM_PFX(gcSmiInitGdtr):
             DQ      0\r
 \r
 global ASM_PFX(SmmStartup)\r
+\r
+BITS 16\r
 ASM_PFX(SmmStartup):\r
-    DB      0x66, 0xb8\r
-ASM_PFX(gSmmCr3): DD 0\r
+    mov     eax, 0x80000001             ; read capability\r
+    cpuid\r
+    mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
+    and     ebx, BIT20                  ; extract NX capability bit\r
+    shr     ebx, 9                      ; shift bit to IA32_EFER.NXE[BIT11] position\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr3):\r
     mov     cr3, eax\r
-    DB      0x67, 0x66\r
-    lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
-    DB      0x66, 0xb8\r
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
+    DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr4): DD 0\r
     mov     cr4, eax\r
-    DB      0x66, 0xb8\r
+    mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
+    rdmsr\r
+    or      eax, ebx                    ; set NXE bit if NX is available\r
+    wrmsr\r
+    DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr0): DD 0\r
-    DB      0xbf, PROTECT_MODE_DS, 0    ; mov di, PROTECT_MODE_DS\r
+    mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
-    DB      0x66, 0xea                   ; jmp far [ptr48]\r
+    DB      0x66, 0xea                  ; jmp far [ptr48]\r
 ASM_PFX(gSmmJmpAddr):\r
     DD      @32bit\r
     DW      PROTECT_MODE_CS\r
+\r
+BITS 32\r
 @32bit:\r
     mov     ds, edi\r
     mov     es, edi\r
@@ -85,4 +97,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
     mov     byte [eax], 1\r
     pop     eax\r
     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]\r
-    END\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+    ret\r