UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMM

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / MpService.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 620b0136c5cfc2447442674de2f42f9214d8faf2..185cb3d5935fe92ebf79a785487c392e080a0d69 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -1,7 +1,7 @@
 /** @file\r
 SMM MP service implementation\r
 \r
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -943,7 +943,7 @@ SmmStartupThisAp (
 }\r
 \r
 /**\r
-  This funciton sets DR6 & DR7 according to SMM save state, before running SMM C code.\r
+  This function sets DR6 & DR7 according to SMM save state, before running SMM C code.\r
   They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.\r
 \r
   NOTE: It might not be appreciated in runtime since it might\r
@@ -961,7 +961,7 @@ CpuSmmDebugEntry (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
   \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       AsmWriteDr6 (CpuSaveState->x86._DR6);\r
       AsmWriteDr7 (CpuSaveState->x86._DR7);\r
@@ -973,7 +973,7 @@ CpuSmmDebugEntry (
 }\r
 \r
 /**\r
-  This funciton restores DR6 & DR7 to SMM save state.\r
+  This function restores DR6 & DR7 to SMM save state.\r
 \r
   NOTE: It might not be appreciated in runtime since it might\r
         conflict with OS debugging facilities. Turn them off in RELEASE.\r
@@ -990,7 +990,7 @@ CpuSmmDebugExit (
   SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
 \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuIndex];\r
+    CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();\r
       CpuSaveState->x86._DR6 = (UINT32)AsmReadDr6 ();\r
@@ -1019,6 +1019,7 @@ SmiRendezvous (
   BOOLEAN           BspInProgress;\r
   UINTN             Index;\r
   UINTN             Cr2;\r
+  BOOLEAN           XdDisableFlag;\r
 \r
   //\r
   // Save Cr2 because Page Fault exception in SMM may override its value\r
@@ -1078,9 +1079,14 @@ SmiRendezvous (
     }\r
 \r
     //\r
-    // Try to enable NX\r
+    // Try to enable XD\r
     //\r
+    XdDisableFlag = FALSE;\r
     if (mXdSupported) {\r
+      if ((AsmReadMsr64 (MSR_IA32_MISC_ENABLE) & B_XD_DISABLE_BIT) != 0) {\r
+        XdDisableFlag = TRUE;\r
+        AsmMsrAnd64 (MSR_IA32_MISC_ENABLE, ~B_XD_DISABLE_BIT);\r
+      }\r
       ActivateXd ();\r
     }\r
 \r
@@ -1152,7 +1158,6 @@ SmiRendezvous (
         // BSP Handler is always called with a ValidSmi == TRUE\r
         //\r
         BSPHandler (CpuIndex, mSmmMpSyncData->EffectiveSyncMode);\r
-\r
       } else {\r
         APHandler (CpuIndex, ValidSmi, mSmmMpSyncData->EffectiveSyncMode);\r
       }\r
@@ -1165,6 +1170,13 @@ SmiRendezvous (
     //\r
     while (mSmmMpSyncData->AllCpusInSync) {\r
       CpuPause ();\r
+     }\r
+\r
+    //\r
+    // Restore XD\r
+    //\r
+    if (XdDisableFlag) {\r
+      AsmMsrOr64 (MSR_IA32_MISC_ENABLE, B_XD_DISABLE_BIT);\r
     }\r
   }\r
 \r