/** @file\r
SMM MP service implementation\r
\r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
\r
/**\r
Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL\r
- \r
+\r
@retval TRUE Os enable lmce.\r
@retval FALSE Os not enable lmce.\r
\r
}\r
\r
/**\r
- Return if Local machine check exception signaled. \r
+ Return if Local machine check exception signaled.\r
\r
- Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was \r
+ Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was\r
delivered to only the logical processor.\r
\r
@retval TRUE LMCE was signaled.\r
Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;\r
}\r
\r
+ Pdpte = (UINT64*)PageTable;\r
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);\r
GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;\r
- Pdpte = (UINT64*)PageTable;\r
for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
}\r
}\r
\r
+ if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) {\r
+ Pte = (UINT64*)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
+ if ((Pte[0] & IA32_PG_PS) == 0) {\r
+ // 4K-page entries are already mapped. Just hide the first one anyway.\r
+ Pte = (UINT64*)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
+ Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0\r
+ } else {\r
+ // Create 4K-page entries\r
+ Pages = (UINTN)AllocatePageTableMemory (1);\r
+ ASSERT (Pages != 0);\r
+\r
+ Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r
+\r
+ Pte = (UINT64*)Pages;\r
+ PageAddress = 0;\r
+ Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left\r
+ for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {\r
+ PageAddress += EFI_PAGE_SIZE;\r
+ Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
+ }\r
+ }\r
+ }\r
+\r
return (UINT32)(UINTN)PageTable;\r
}\r
\r
)\r
{\r
SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
- \r
+\r
if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
ASSERT(CpuIndex < mMaxNumberOfCpus);\r
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r