UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / PiSmmCpuDxeSmm.c

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 282d2e69817c2a4f9f0caecf38bfd9ebf514f9fc..fbf74e8d90f953cea4cd69da3bccadd1c6dcc609 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1,7 +1,7 @@
 /** @file\r
 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.\r
 \r
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
 \r
 This program and the accompanying materials\r
@@ -76,6 +76,15 @@ EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {
   SmmWriteSaveState\r
 };\r
 \r
+///\r
+/// SMM Memory Attribute Protocol instance\r
+///\r
+EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute  = {\r
+  EdkiiSmmGetMemoryAttributes,\r
+  EdkiiSmmSetMemoryAttributes,\r
+  EdkiiSmmClearMemoryAttributes\r
+};\r
+\r
 EFI_CPU_INTERRUPT_HANDLER   mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
 \r
 //\r
@@ -116,6 +125,12 @@ UINTN                    mSmmCpuSmramRangeCount;
 \r
 UINT8                    mPhysicalAddressBits;\r
 \r
+//\r
+// Control register contents saved for SMM S3 resume state initialization.\r
+//\r
+UINT32                   mSmmCr0;\r
+UINT32                   mSmmCr4;\r
+\r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
 \r
@@ -396,9 +411,11 @@ SmmRelocateBases (
   //\r
   // Patch ASM code template with current CR0, CR3, and CR4 values\r
   //\r
-  gSmmCr0 = (UINT32)AsmReadCr0 ();\r
-  gSmmCr3 = (UINT32)AsmReadCr3 ();\r
-  gSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  mSmmCr0 = (UINT32)AsmReadCr0 ();\r
+  PatchInstructionX86 (gPatchSmmCr0, mSmmCr0, 4);\r
+  PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);\r
+  mSmmCr4 = (UINT32)AsmReadCr4 ();\r
+  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);\r
 \r
   //\r
   // Patch GDTR for SMM base relocation\r
@@ -533,6 +550,12 @@ PiCpuSmmEntry (
   UINTN                      ModelId;\r
   UINT32                     Cr3;\r
 \r
+  //\r
+  // Initialize address fixup\r
+  //\r
+  PiSmmCpuSmmInitFixupAddress ();\r
+  PiSmmCpuSmiEntryFixupAddress ();\r
+\r
   //\r
   // Initialize Debug Agent to support source level debug in SMM code\r
   //\r
@@ -546,13 +569,6 @@ PiCpuSmmEntry (
     EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT\r
     );\r
 \r
-  //\r
-  // Fix segment address of the long-mode-switch jump\r
-  //\r
-  if (sizeof (UINTN) == sizeof (UINT64)) {\r
-    gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;\r
-  }\r
-\r
   //\r
   // Find out SMRR Base and SMRR Size\r
   //\r
@@ -832,7 +848,11 @@ PiCpuSmmEntry (
   //\r
   // Set SMI stack for SMM base relocation\r
   //\r
-  gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));\r
+  PatchInstructionX86 (\r
+    gPatchSmmInitStack,\r
+    (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),\r
+    sizeof (UINTN)\r
+    );\r
 \r
   //\r
   // Initialize IDT\r
@@ -893,6 +913,17 @@ PiCpuSmmEntry (
                     );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
+  //\r
+  // Install the SMM Memory Attribute Protocol into SMM protocol database\r
+  //\r
+  Status = gSmst->SmmInstallProtocolInterface (\r
+                    &mSmmCpuHandle,\r
+                    &gEdkiiSmmMemoryAttributeProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    &mSmmMemoryAttribute\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
   //\r
   // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.\r
   //\r