typedef union {\r
struct {\r
// enable shadow stacks\r
- UINT32 SH_STK_ENP:1;\r
+ UINT32 SH_STK_ENP : 1;\r
// enable the WRSS{D,Q}W instructions.\r
- UINT32 WR_SHSTK_EN:1;\r
+ UINT32 WR_SHSTK_EN : 1;\r
// enable tracking of indirect call/jmp targets to be ENDBRANCH instruction.\r
- UINT32 ENDBR_EN:1;\r
+ UINT32 ENDBR_EN : 1;\r
// enable legacy compatibility treatment for indirect call/jmp tracking.\r
- UINT32 LEG_IW_EN:1;\r
+ UINT32 LEG_IW_EN : 1;\r
// enable use of no-track prefix on indirect call/jmp.\r
- UINT32 NO_TRACK_EN:1;\r
+ UINT32 NO_TRACK_EN : 1;\r
// disable suppression of CET indirect branch tracking on legacy compatibility.\r
- UINT32 SUPPRESS_DIS:1;\r
- UINT32 RSVD:4;\r
+ UINT32 SUPPRESS_DIS : 1;\r
+ UINT32 RSVD : 4;\r
// indirect branch tracking is suppressed.\r
// This bit can be written to 1 only if TRACKER is written as IDLE.\r
- UINT32 SUPPRESS:1;\r
+ UINT32 SUPPRESS : 1;\r
// Value of the endbranch state machine\r
// Values: IDLE (0), WAIT_FOR_ENDBRANCH(1).\r
- UINT32 TRACKER:1;\r
+ UINT32 TRACKER : 1;\r
// linear address of a bitmap in memory indicating valid\r
// pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled\r
// and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on\r
// parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are\r
// reserved and must be 0. This value is extended by 12 bits at the low end to form the base address\r
// (this automatically aligns the address on a 4-Kbyte boundary).\r
- UINT32 EB_LEG_BITMAP_BASE_low:12;\r
- UINT32 EB_LEG_BITMAP_BASE_high:32;\r
+ UINT32 EB_LEG_BITMAP_BASE_low : 12;\r
+ UINT32 EB_LEG_BITMAP_BASE_high : 32;\r
} Bits;\r
- UINT64 Uint64;\r
+ UINT64 Uint64;\r
} MSR_IA32_CET;\r
\r
//\r
// MSRs required for configuration of SMM Code Access Check\r
//\r
-#define EFI_MSR_SMM_MCA_CAP 0x17D\r
-#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
+#define EFI_MSR_SMM_MCA_CAP 0x17D\r
+#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
\r
-#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
-#define SMM_CODE_CHK_EN_BIT BIT2\r
+#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0\r
+#define SMM_CODE_CHK_EN_BIT BIT2\r
\r
///\r
/// Page Table Entry\r
///\r
-#define IA32_PG_P BIT0\r
-#define IA32_PG_RW BIT1\r
-#define IA32_PG_U BIT2\r
-#define IA32_PG_WT BIT3\r
-#define IA32_PG_CD BIT4\r
-#define IA32_PG_A BIT5\r
-#define IA32_PG_D BIT6\r
-#define IA32_PG_PS BIT7\r
-#define IA32_PG_PAT_2M BIT12\r
-#define IA32_PG_PAT_4K IA32_PG_PS\r
-#define IA32_PG_PMNT BIT62\r
-#define IA32_PG_NX BIT63\r
-\r
-#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
+#define IA32_PG_P BIT0\r
+#define IA32_PG_RW BIT1\r
+#define IA32_PG_U BIT2\r
+#define IA32_PG_WT BIT3\r
+#define IA32_PG_CD BIT4\r
+#define IA32_PG_A BIT5\r
+#define IA32_PG_D BIT6\r
+#define IA32_PG_PS BIT7\r
+#define IA32_PG_PAT_2M BIT12\r
+#define IA32_PG_PAT_4K IA32_PG_PS\r
+#define IA32_PG_PMNT BIT62\r
+#define IA32_PG_NX BIT63\r
+\r
+#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
//\r
// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
// X64 PAE PDPTE does not have such restriction\r
//\r
-#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)\r
\r
-#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
+#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
\r
#define PAGING_4K_MASK 0xFFF\r
#define PAGING_2M_MASK 0x1FFFFF\r
\r
#define PAGING_PAE_INDEX_MASK 0x1FF\r
\r
-#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
+#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
\r
-#define SMRR_MAX_ADDRESS BASE_4GB\r
+#define SMRR_MAX_ADDRESS BASE_4GB\r
\r
typedef enum {\r
PageNone,\r
} PAGE_ATTRIBUTE;\r
\r
typedef struct {\r
- PAGE_ATTRIBUTE Attribute;\r
- UINT64 Length;\r
- UINT64 AddressMask;\r
+ PAGE_ATTRIBUTE Attribute;\r
+ UINT64 Length;\r
+ UINT64 AddressMask;\r
} PAGE_ATTRIBUTE_TABLE;\r
\r
//\r
// Size of Task-State Segment defined in IA32 Manual\r
//\r
-#define TSS_SIZE 104\r
-#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP\r
-#define TSS_X64_IST1_OFFSET 36\r
-#define TSS_IA32_CR3_OFFSET 28\r
-#define TSS_IA32_ESP_OFFSET 56\r
-#define TSS_IA32_SSP_OFFSET 104\r
+#define TSS_SIZE 104\r
+#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP\r
+#define TSS_X64_IST1_OFFSET 36\r
+#define TSS_IA32_CR3_OFFSET 28\r
+#define TSS_IA32_ESP_OFFSET 56\r
+#define TSS_IA32_SSP_OFFSET 104\r
\r
-#define CR0_WP BIT16\r
+#define CR0_WP BIT16\r
\r
//\r
// Code select value\r
//\r
-#define PROTECT_MODE_CODE_SEGMENT 0x08\r
-#define LONG_MODE_CODE_SEGMENT 0x38\r
+#define PROTECT_MODE_CODE_SEGMENT 0x08\r
+#define LONG_MODE_CODE_SEGMENT 0x38\r
\r
//\r
// The size 0x20 must be bigger than\r
//\r
#define BACK_BUF_SIZE 0x20\r
\r
-#define EXCEPTION_VECTOR_NUMBER 0x20\r
+#define EXCEPTION_VECTOR_NUMBER 0x20\r
\r
-#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
+#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
\r
-typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
-#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
-#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
-#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
+typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
+#define ARRIVAL_EXCEPTION_BLOCKED 0x1\r
+#define ARRIVAL_EXCEPTION_DELAYED 0x2\r
+#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4\r
\r
//\r
// Wrapper used to convert EFI_AP_PROCEDURE2 and EFI_AP_PROCEDURE.\r
//\r
typedef struct {\r
- EFI_AP_PROCEDURE Procedure;\r
- VOID *ProcedureArgument;\r
+ EFI_AP_PROCEDURE Procedure;\r
+ VOID *ProcedureArgument;\r
} PROCEDURE_WRAPPER;\r
\r
#define PROCEDURE_TOKEN_SIGNATURE SIGNATURE_32 ('P', 'R', 'T', 'S')\r
\r
typedef struct {\r
- UINTN Signature;\r
- LIST_ENTRY Link;\r
+ UINTN Signature;\r
+ LIST_ENTRY Link;\r
\r
- SPIN_LOCK *SpinLock;\r
- volatile UINT32 RunningApCount;\r
+ SPIN_LOCK *SpinLock;\r
+ volatile UINT32 RunningApCount;\r
} PROCEDURE_TOKEN;\r
\r
#define PROCEDURE_TOKEN_FROM_LINK(a) CR (a, PROCEDURE_TOKEN, Link, PROCEDURE_TOKEN_SIGNATURE)\r
#define TOKEN_BUFFER_SIGNATURE SIGNATURE_32 ('T', 'K', 'B', 'S')\r
\r
typedef struct {\r
- UINTN Signature;\r
- LIST_ENTRY Link;\r
+ UINTN Signature;\r
+ LIST_ENTRY Link;\r
\r
- UINT8 *Buffer;\r
+ UINT8 *Buffer;\r
} TOKEN_BUFFER;\r
\r
#define TOKEN_BUFFER_FROM_LINK(a) CR (a, TOKEN_BUFFER, Link, TOKEN_BUFFER_SIGNATURE)\r
#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')\r
\r
typedef struct {\r
- UINTN Signature;\r
+ UINTN Signature;\r
\r
- EFI_HANDLE SmmCpuHandle;\r
+ EFI_HANDLE SmmCpuHandle;\r
\r
- EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
- SMM_CPU_OPERATION *Operation;\r
- UINTN *CpuSaveStateSize;\r
- VOID **CpuSaveState;\r
+ EFI_PROCESSOR_INFORMATION *ProcessorInfo;\r
+ SMM_CPU_OPERATION *Operation;\r
+ UINTN *CpuSaveStateSize;\r
+ VOID **CpuSaveState;\r
\r
- EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
- EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
- EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
+ EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];\r
+ EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;\r
+ EFI_SMM_ENTRY_POINT SmmCoreEntry;\r
\r
- EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
+ EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;\r
\r
- PROCEDURE_WRAPPER *ApWrapperFunc;\r
- LIST_ENTRY TokenList;\r
- LIST_ENTRY *FirstFreeToken;\r
+ PROCEDURE_WRAPPER *ApWrapperFunc;\r
+ LIST_ENTRY TokenList;\r
+ LIST_ENTRY *FirstFreeToken;\r
} SMM_CPU_PRIVATE_DATA;\r
\r
extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;\r
-extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
-extern UINTN mMaxNumberOfCpus;\r
-extern UINTN mNumberOfCpus;\r
-extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
-extern EFI_MM_MP_PROTOCOL mSmmMp;\r
-extern UINTN mInternalCr3;\r
+extern CPU_HOT_PLUG_DATA mCpuHotPlugData;\r
+extern UINTN mMaxNumberOfCpus;\r
+extern UINTN mNumberOfCpus;\r
+extern EFI_SMM_CPU_PROTOCOL mSmmCpu;\r
+extern EFI_MM_MP_PROTOCOL mSmmMp;\r
+extern UINTN mInternalCr3;\r
\r
///\r
/// The mode of the CPU at the time an SMI occurs\r
EFI_STATUS\r
EFIAPI\r
SmmReadSaveState (\r
- IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
- IN UINTN Width,\r
- IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
- IN UINTN CpuIndex,\r
- OUT VOID *Buffer\r
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
+ IN UINTN Width,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN CpuIndex,\r
+ OUT VOID *Buffer\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmWriteSaveState (\r
- IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
- IN UINTN Width,\r
- IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
- IN UINTN CpuIndex,\r
- IN CONST VOID *Buffer\r
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,\r
+ IN UINTN Width,\r
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,\r
+ IN UINTN CpuIndex,\r
+ IN CONST VOID *Buffer\r
);\r
\r
/**\r
IN CONST VOID *Buffer\r
);\r
\r
-extern CONST UINT8 gcSmmInitTemplate[];\r
-extern CONST UINT16 gcSmmInitSize;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;\r
-extern UINT32 mSmmCr0;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r
-extern UINT32 mSmmCr4;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;\r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported;\r
-extern BOOLEAN mCetSupported;\r
+extern CONST UINT8 gcSmmInitTemplate[];\r
+extern CONST UINT16 gcSmmInitSize;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;\r
+extern UINT32 mSmmCr0;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;\r
+extern UINT32 mSmmCr4;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;\r
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;\r
+X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported;\r
+extern BOOLEAN mCetSupported;\r
\r
/**\r
Semaphore operation for all processor relocate SMMBase.\r
/// The type of SMM CPU Information\r
///\r
typedef struct {\r
- SPIN_LOCK *Busy;\r
- volatile EFI_AP_PROCEDURE2 Procedure;\r
- volatile VOID *Parameter;\r
- volatile UINT32 *Run;\r
- volatile BOOLEAN *Present;\r
- PROCEDURE_TOKEN *Token;\r
- EFI_STATUS *Status;\r
+ SPIN_LOCK *Busy;\r
+ volatile EFI_AP_PROCEDURE2 Procedure;\r
+ volatile VOID *Parameter;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
+ PROCEDURE_TOKEN *Token;\r
+ EFI_STATUS *Status;\r
} SMM_CPU_DATA_BLOCK;\r
\r
typedef enum {\r
VOID *StartupProcArgs;\r
} SMM_DISPATCHER_MP_SYNC_DATA;\r
\r
-#define SMM_PSD_OFFSET 0xfb00\r
+#define SMM_PSD_OFFSET 0xfb00\r
\r
///\r
/// All global semaphores' pointer\r
///\r
typedef struct {\r
- volatile UINT32 *Counter;\r
- volatile BOOLEAN *InsideSmm;\r
- volatile BOOLEAN *AllCpusInSync;\r
- SPIN_LOCK *PFLock;\r
- SPIN_LOCK *CodeAccessCheckLock;\r
+ volatile UINT32 *Counter;\r
+ volatile BOOLEAN *InsideSmm;\r
+ volatile BOOLEAN *AllCpusInSync;\r
+ SPIN_LOCK *PFLock;\r
+ SPIN_LOCK *CodeAccessCheckLock;\r
} SMM_CPU_SEMAPHORE_GLOBAL;\r
\r
///\r
/// All semaphores for each processor\r
///\r
typedef struct {\r
- SPIN_LOCK *Busy;\r
- volatile UINT32 *Run;\r
- volatile BOOLEAN *Present;\r
- SPIN_LOCK *Token;\r
+ SPIN_LOCK *Busy;\r
+ volatile UINT32 *Run;\r
+ volatile BOOLEAN *Present;\r
+ SPIN_LOCK *Token;\r
} SMM_CPU_SEMAPHORE_CPU;\r
\r
///\r
/// All semaphores' information\r
///\r
typedef struct {\r
- SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
- SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
+ SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;\r
+ SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;\r
} SMM_CPU_SEMAPHORES;\r
\r
-extern IA32_DESCRIPTOR gcSmiGdtr;\r
-extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r
-extern UINTN mGdtBufferSize;\r
-extern IA32_DESCRIPTOR gcSmiIdtr;\r
-extern VOID *gcSmiIdtrPtr;\r
-extern UINT64 gPhyMask;\r
-extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
-extern UINTN mSmmStackArrayBase;\r
-extern UINTN mSmmStackArrayEnd;\r
-extern UINTN mSmmStackSize;\r
-extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
-extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
-extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
-extern UINTN mSemaphoreSize;\r
-extern SPIN_LOCK *mPFLock;\r
-extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
-extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
-extern UINTN mSmmCpuSmramRangeCount;\r
-extern UINT8 mPhysicalAddressBits;\r
+extern IA32_DESCRIPTOR gcSmiGdtr;\r
+extern EFI_PHYSICAL_ADDRESS mGdtBuffer;\r
+extern UINTN mGdtBufferSize;\r
+extern IA32_DESCRIPTOR gcSmiIdtr;\r
+extern VOID *gcSmiIdtrPtr;\r
+extern UINT64 gPhyMask;\r
+extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;\r
+extern UINTN mSmmStackArrayBase;\r
+extern UINTN mSmmStackArrayEnd;\r
+extern UINTN mSmmStackSize;\r
+extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;\r
+extern IA32_DESCRIPTOR gcSmiInitGdtr;\r
+extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;\r
+extern UINTN mSemaphoreSize;\r
+extern SPIN_LOCK *mPFLock;\r
+extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;\r
+extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;\r
+extern UINTN mSmmCpuSmramRangeCount;\r
+extern UINT8 mPhysicalAddressBits;\r
\r
//\r
// Copy of the PcdPteMemoryEncryptionAddressOrMask\r
**/\r
UINT32\r
Gen4GPageTable (\r
- IN BOOLEAN Is32BitPageTable\r
+ IN BOOLEAN Is32BitPageTable\r
);\r
\r
-\r
/**\r
Initialize global data for MP synchronization.\r
\r
**/\r
UINT32\r
InitializeMpServiceData (\r
- IN VOID *Stacks,\r
- IN UINTN StackSize,\r
- IN UINTN ShadowStackSize\r
+ IN VOID *Stacks,\r
+ IN UINTN StackSize,\r
+ IN UINTN ShadowStackSize\r
);\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
IsSyncTimerTimeout (\r
- IN UINT64 Timer\r
+ IN UINT64 Timer\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
InitializeIdtIst (\r
- IN EFI_EXCEPTION_TYPE ExceptionType,\r
- IN UINT8 Ist\r
+ IN EFI_EXCEPTION_TYPE ExceptionType,\r
+ IN UINT8 Ist\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmStartupThisAp (\r
- IN EFI_AP_PROCEDURE Procedure,\r
- IN UINTN CpuIndex,\r
- IN OUT VOID *ProcArguments OPTIONAL\r
+ IN EFI_AP_PROCEDURE Procedure,\r
+ IN UINTN CpuIndex,\r
+ IN OUT VOID *ProcArguments OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmBlockingStartupThisAp (\r
- IN EFI_AP_PROCEDURE Procedure,\r
- IN UINTN CpuIndex,\r
- IN OUT VOID *ProcArguments OPTIONAL\r
+ IN EFI_AP_PROCEDURE Procedure,\r
+ IN UINTN CpuIndex,\r
+ IN OUT VOID *ProcArguments OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmSetMemoryAttributes (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmClearMemoryAttributes (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
/**\r
**/\r
VOID\r
FindSmramInfo (\r
- OUT UINT32 *SmrrBase,\r
- OUT UINT32 *SmrrSize\r
+ OUT UINT32 *SmrrBase,\r
+ OUT UINT32 *SmrrSize\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SmiPFHandler (\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_SYSTEM_CONTEXT SystemContext\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_SYSTEM_CONTEXT SystemContext\r
);\r
\r
/**\r
**/\r
VOID\r
InitMsrSpinLockByIndex (\r
- IN UINT32 MsrIndex\r
+ IN UINT32 MsrIndex\r
);\r
\r
/**\r
**/\r
VOID\r
DumpModuleInfoByIp (\r
- IN UINTN CallerIpAddress\r
+ IN UINTN CallerIpAddress\r
);\r
\r
/**\r
**/\r
VOID\r
GetPageTable (\r
- OUT UINTN *Base,\r
- OUT BOOLEAN *FiveLevels OPTIONAL\r
+ OUT UINTN *Base,\r
+ OUT BOOLEAN *FiveLevels OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmSetMemoryAttributesEx (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- OUT BOOLEAN *IsSplitted OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ OUT BOOLEAN *IsSplitted OPTIONAL\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SmmClearMemoryAttributesEx (\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes,\r
- OUT BOOLEAN *IsSplitted OPTIONAL\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes,\r
+ OUT BOOLEAN *IsSplitted OPTIONAL\r
);\r
\r
/**\r
**/\r
VOID *\r
AllocatePageTableMemory (\r
- IN UINTN Pages\r
+ IN UINTN Pages\r
);\r
\r
/**\r
**/\r
VOID *\r
AllocateCodePages (\r
- IN UINTN Pages\r
+ IN UINTN Pages\r
);\r
\r
/**\r
**/\r
VOID *\r
AllocateAlignedCodePages (\r
- IN UINTN Pages,\r
- IN UINTN Alignment\r
+ IN UINTN Pages,\r
+ IN UINTN Alignment\r
);\r
\r
-\r
//\r
// S3 related global variable and function prototype.\r
//\r
\r
-extern BOOLEAN mSmmS3Flag;\r
+extern BOOLEAN mSmmS3Flag;\r
\r
/**\r
Initialize SMM S3 resume state structure used during S3 Resume.\r
**/\r
EFI_STATUS\r
SetShadowStack (\r
- IN UINTN Cr3,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN UINTN Cr3,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
SetNotPresentPage (\r
- IN UINTN Cr3,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length\r
+ IN UINTN Cr3,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EdkiiSmmSetMemoryAttributes (\r
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EdkiiSmmClearMemoryAttributes (\r
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 Attributes\r
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 Attributes\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
EdkiiSmmGetMemoryAttributes (\r
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
- IN UINT64 Length,\r
- IN UINT64 *Attributes\r
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
+ IN UINT64 Length,\r
+ IN UINT64 *Attributes\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
PiSmmCpuSmmInitFixupAddress (\r
- );\r
+ );\r
\r
/**\r
This function fixes up the address of the global variable or function\r
VOID\r
EFIAPI\r
PiSmmCpuSmiEntryFixupAddress (\r
- );\r
+ );\r
\r
/**\r
This function reads CR2 register when on-demand paging is enabled\r
**/\r
EFI_STATUS\r
InternalSmmStartupThisAp (\r
- IN EFI_AP_PROCEDURE2 Procedure,\r
- IN UINTN CpuIndex,\r
- IN OUT VOID *ProcArguments OPTIONAL,\r
- IN OUT MM_COMPLETION *Token,\r
- IN UINTN TimeoutInMicroseconds,\r
- IN OUT EFI_STATUS *CpuStatus\r
+ IN EFI_AP_PROCEDURE2 Procedure,\r
+ IN UINTN CpuIndex,\r
+ IN OUT VOID *ProcArguments OPTIONAL,\r
+ IN OUT MM_COMPLETION *Token,\r
+ IN UINTN TimeoutInMicroseconds,\r
+ IN OUT EFI_STATUS *CpuStatus\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsTokenInUse (\r
- IN SPIN_LOCK *Token\r
+ IN SPIN_LOCK *Token\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsPresentAp (\r
- IN UINTN CpuIndex\r
+ IN UINTN CpuIndex\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
InternalSmmStartupAllAPs (\r
- IN EFI_AP_PROCEDURE2 Procedure,\r
- IN UINTN TimeoutInMicroseconds,\r
- IN OUT VOID *ProcedureArguments OPTIONAL,\r
- IN OUT MM_COMPLETION *Token,\r
- IN OUT EFI_STATUS *CPUStatus\r
+ IN EFI_AP_PROCEDURE2 Procedure,\r
+ IN UINTN TimeoutInMicroseconds,\r
+ IN OUT VOID *ProcedureArguments OPTIONAL,\r
+ IN OUT MM_COMPLETION *Token,\r
+ IN OUT EFI_STATUS *CPUStatus\r
);\r
\r
/**\r
**/\r
EFI_STATUS\r
RegisterStartupProcedure (\r
- IN EFI_AP_PROCEDURE Procedure,\r
- IN OUT VOID *ProcedureArguments OPTIONAL\r
+ IN EFI_AP_PROCEDURE Procedure,\r
+ IN OUT VOID *ProcedureArguments OPTIONAL\r
);\r
\r
/**\r
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