UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr3" with PatchInstructionX86()

[mirror_edk2.git] / UefiCpuPkg / PiSmmCpuDxeSmm / X64 / SmmInit.nasm

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 9d05e2cb0582b3fd648fcea066d0a85654dc8c83..2df22a1f6cd1591a8aef3100d0de46c93809b731 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -22,7 +22,7 @@ extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)\r
 extern ASM_PFX(mSmmRelocationOriginalAddress)\r
 \r
-global ASM_PFX(gSmmCr3)\r
+global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gSmmCr4)\r
 global ASM_PFX(gSmmCr0)\r
 global ASM_PFX(gSmmJmpAddr)\r
@@ -41,26 +41,35 @@ ASM_PFX(gcSmiInitGdtr):
             DQ      0\r
 \r
 global ASM_PFX(SmmStartup)\r
+\r
+BITS 16\r
 ASM_PFX(SmmStartup):\r
-    DB      0x66, 0xb8                   ; mov eax, imm32\r
-ASM_PFX(gSmmCr3): DD 0\r
-    mov     cr3, rax\r
-    DB      0x66, 0x2e\r
-    lgdt    [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
+    mov     eax, 0x80000001             ; read capability\r
+    cpuid\r
+    mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
+    mov     eax, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmCr3):\r
+    mov     cr3, eax\r
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
     DB      0x66, 0xb8                   ; mov eax, imm32\r
 ASM_PFX(gSmmCr4): DD 0\r
     or      ah,  2                      ; enable XMM registers access\r
-    mov     cr4, rax\r
-    DB      0x66\r
+    mov     cr4, eax\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
-    or      ah, 1                       ; set LME bit\r
+    or      ah, BIT0                    ; set LME bit\r
+    test    ebx, BIT20                  ; check NXE capability\r
+    jz      .1\r
+    or      ah, BIT3                    ; set NXE bit\r
+.1:\r
     wrmsr\r
     DB      0x66, 0xb8                   ; mov eax, imm32\r
 ASM_PFX(gSmmCr0): DD 0\r
-    mov     cr0, rax                    ; enable protected mode & paging\r
+    mov     cr0, eax                    ; enable protected mode & paging\r
     DB      0x66, 0xea                   ; far jmp to long mode\r
-ASM_PFX(gSmmJmpAddr): DQ @LongMode\r
+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode\r
+\r
+BITS 64\r
 @LongMode:                              ; long-mode starts here\r
     DB      0x48, 0xbc                   ; mov rsp, imm64\r
 ASM_PFX(gSmmInitStack): DQ 0\r
@@ -99,7 +108,7 @@ ASM_PFX(gcSmmInitTemplate):
     sub ebp, 0x30000\r
     jmp ebp\r
 @L1:\r
-    DQ      ASM_PFX(SmmStartup)\r
+    DQ     0; ASM_PFX(SmmStartup)\r
 \r
 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r
 \r
@@ -128,3 +137,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
     ;\r
     db      0xff, 0x25\r
 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0\r
+\r
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r
+    lea    rax, [@LongMode]\r
+    lea    rcx, [ASM_PFX(gSmmJmpAddr)]\r
+    mov    qword [rcx], rax\r
+\r
+    lea    rax, [ASM_PFX(SmmStartup)]\r
+    lea    rcx, [@L1]\r
+    mov    qword [rcx], rax\r
+    ret\r