UefiPayloadPkg: Enhance UEFI payload for coreboot and Slim Bootloader

[mirror_edk2.git] / UefiPayloadPkg / Library / PlatformBootManagerLib / PlatformConsole.h

diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h
new file mode 100644 (file)
index 0000000..68bdf5e
--- /dev/null
+++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h
@@ -0,0 +1,70 @@
+/** @file\r
+Head file for BDS Platform specific code\r
+\r
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#ifndef _PLATFORM_CONSOLE_H\r
+#define _PLATFORM_CONSOLE_H\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Protocol/PciIo.h>\r
+\r
+#define IS_PCI_ISA_PDECODE(_p)        IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)\r
+#define IS_PCI_16550SERIAL(_p)        IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+\r
+//\r
+// Type definitions\r
+//\r
+\r
+//\r
+// Platform Root Bridge\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(\r
+  IN EFI_HANDLE            Handle,\r
+  IN VOID                 *Instance,\r
+  IN VOID                 *Context\r
+);\r
+\r
+/**\r
+  @param[in]  Handle - Handle of PCI device instance\r
+  @param[in]  PciIo - PCI IO protocol instance\r
+  @param[in]  Pci - PCI Header register block\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(\r
+  IN EFI_HANDLE           Handle,\r
+  IN EFI_PCI_IO_PROTOCOL  *PciIo,\r
+  IN PCI_TYPE00           *Pci\r
+);\r
+\r
+/**\r
+  Platform console init. Include the platform firmware vendor, revision\r
+  and so crc check.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformConsoleInit (\r
+  VOID\r
+);\r
+\r
+#endif\r