+++ /dev/null
-/**************************************************************************;\r
-;* *;\r
-;* *;\r
-;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
-;* Family of Customer Reference Boards. *;\r
-;* *;\r
-;* *;\r
-;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r
-;\r
-; SPDX-License-Identifier: BSD-2-Clause-Patent\r
-;\r
-;* *;\r
-;* *;\r
-;**************************************************************************/\r
-\r
-\r
-// Define various SMBus PCI Configuration Space Registers.\r
-\r
-OperationRegion(SMBP,PCI_Config,0x40,0xC0)\r
-Field(SMBP,DWordAcc,NoLock,Preserve)\r
-{\r
- , 2,\r
- I2CE, 1\r
-}\r
-\r
-// SMBus Send Byte - This function will write a single byte of\r
-// data to a specific Slave Device per SMBus Send Byte Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Data\r
-// Return: Success = 1\r
-// Failure = 0\r
-\r
- Method(SSXB,2,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
-\r
- // Step 1: Confirm the ICHx SMBus is ready to perform\r
- // communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0)\r
- }\r
-\r
- // Step 2: Initiate a Send Byte.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Arg0,TXSA) // Write Address in TXSA.\r
- Store(Arg1,HCOM) // Data in HCOM.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 001 = Byte Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x48,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP)\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r
- Return(1) // Return Success.\r
- }\r
-\r
- Return(0)\r
-}\r
-\r
-// SMBus Receive Byte - This function will write a single byte\r
-// of data to a specific Slave Device per SMBus Receive Byte\r
-// Protocol.\r
-// Arg0 = Address\r
-// Return: Success = Byte-Size Value\r
-// Failure = Word-Size Value = FFFFh.\r
-\r
-Method(SRXB,1,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform\r
- // communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0xFFFF)\r
- }\r
-\r
- // Step 2: Initiate a Receive Byte.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 001 = Byte Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x44,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP)\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r
- Return(DAT0) // Return Success.\r
- }\r
-\r
- Return(0xFFFF) // Return Failure.\r
-}\r
-\r
-// SMBus Write Byte - This function will write a single byte\r
-// of data to a specific Slave Device per SMBus Write Byte\r
-// Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Arg2 = Data\r
-// Return: Success = 1\r
-// Failure = 0\r
-\r
-Method(SWRB,3,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0)\r
- }\r
-\r
- // Step 2: Initiate a Write Byte.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Arg0,TXSA) // Write Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
- Store(Arg2,DAT0) // Data in DAT0.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 010 = Byte Data Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x48,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP)\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r
- Return(1) // Return Success.\r
- }\r
-\r
- Return(0) // Return Failure.\r
-}\r
-\r
-// SMBus Read Byte - This function will read a single byte of data\r
-// from a specific slave device per SMBus Read Byte Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Return: Success = Byte-Size Value\r
-// Failure = Word-Size Value\r
-\r
-Method(SRDB,2,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0xFFFF)\r
- }\r
-\r
- // Step 2: Initiate a Read Byte.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 010 = Byte Data Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x48,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP)\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others..\r
- Return(DAT0) // Return Success.\r
- }\r
-\r
- Return(0xFFFF) // Return Failure.\r
-}\r
-\r
-// SMBus Write Word - This function will write a single word\r
-// of data to a specific Slave Device per SMBus Write Word\r
-// Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Arg2 = Data (16 bits in size)\r
-// Return: Success = 1\r
-// Failure = 0\r
-\r
-Method(SWRW,3,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0)\r
- }\r
-\r
- // Step 2: Initiate a Write Word.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Arg0,TXSA) // Write Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
- And(Arg2,0xFF,DAT1) // Low byte Data in DAT1.\r
- And(ShiftRight(Arg2,8),0xFF,DAT0) // High byte Data in DAT0.\r
-\r
- // Set the SMBus Host control register to 0x4C.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 011 = Word Data Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x4C,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP())\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r
- Return(1) // Return Success.\r
- }\r
-\r
- Return(0) // Return Failure.\r
-}\r
-\r
-// SMBus Read Word - This function will read a single byte of data\r
-// from a specific slave device per SMBus Read Word Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Return: Success = Word-Size Value\r
-// Failure = Dword-Size Value\r
-\r
-Method(SRDW,2,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0xFFFF)\r
- }\r
-\r
- // Step 2: Initiate a Read Word.\r
-\r
- Store(0,I2CE) // Ensure SMbus Mode.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
-\r
- // Set the SMBus Host control register to 0x4C.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 011 = Word Data Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x4C,HCON)\r
-\r
- // Step 3: Exit the Method correctly.\r
-\r
- If(COMP())\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r
- Return(Or(ShiftLeft(DAT0,8),DAT1)) // Return Success.\r
- }\r
-\r
- Return(0xFFFFFFFF) // Return Failure.\r
-}\r
-\r
-// SMBus Block Write - This function will write an entire block of data\r
-// to a specific slave device per SMBus Block Write Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Arg2 = Buffer of Data to Write\r
-// Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write\r
-// Return: Success = 1\r
-// Failure = 0\r
-\r
-Method(SBLW,4,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0)\r
- }\r
-\r
- // Step 2: Initiate a Block Write.\r
-\r
- Store(Arg3,I2CE) // Select the proper protocol.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Arg0,TXSA) // Write Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
- Store(Sizeof(Arg2),DAT0) // Count in DAT0.\r
- Store(0,Local1) // Init Pointer to Buffer.\r
- Store(DerefOf(Index(Arg2,0)),HBDR) // First Byte in HBD Register.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 101 = Block Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x54,HCON)\r
-\r
- // Step 3: Send the entire Block of Data.\r
-\r
- While(LGreater(Sizeof(Arg2),Local1))\r
- {\r
- // Wait up to 200ms for Host Status to get set.\r
-\r
- Store(4000,Local0) // 4000 * 50us = 200ms.\r
-\r
- While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
- {\r
- Decrement(Local0) // Decrement Count.\r
- Stall(50) // Delay = 50us.\r
- }\r
-\r
- If(LNot(Local0)) // Timeout?\r
- {\r
- KILL() // Yes. Kill Communication.\r
- Return(0) // Return failure.\r
- }\r
-\r
- Store(0x80,HSTS) // Clear Host Status.\r
- Increment(Local1) // Point to Next Byte.\r
-\r
- // Place next byte in HBDR if last byte has not been sent.\r
-\r
- If(LGreater(Sizeof(Arg2),Local1))\r
- {\r
- Store(DerefOf(Index(Arg2,Local1)),HBDR)\r
- }\r
- }\r
-\r
- // Step 4: Exit the Method correctly.\r
-\r
- If(COMP())\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear all status bits.\r
- Return(1) // Return Success.\r
- }\r
-\r
- Return(0) // Return Failure.\r
-}\r
-\r
-// SMBus Block Read - This function will read a block of data from\r
-// a specific slave device per SMBus Block Read Protocol.\r
-// Arg0 = Address\r
-// Arg1 = Command\r
-// Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write\r
-// Return: Success = Data Buffer (First Byte = length)\r
-// Failure = 0\r
-\r
-Method(SBLR,3,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- Name(TBUF, Buffer(256) {})\r
-\r
- // Step 1: Confirm the ICHx SMBus is ready to perform communication.\r
-\r
- If(STRT())\r
- {\r
- Return(0)\r
- }\r
-\r
- // Step 2: Initiate a Block Read.\r
-\r
- Store(Arg2,I2CE) // Select the proper protocol.\r
- Store(0xBF,HSTS) // Clear all but INUSE_STS.\r
- Store(Or(Arg0,1),TXSA) // Read Address in TXSA.\r
- Store(Arg1,HCOM) // Command in HCOM.\r
-\r
- // Set the SMBus Host control register to 0x48.\r
- // Bit 7: = 0 = reserved\r
- // Bit 6: = 1 = start\r
- // Bit 5: = 0 = disregard, I2C related bit\r
- // Bits 4:2: = 101 = Block Protocol\r
- // Bit 1: = 0 = Normal Function\r
- // Bit 0: = 0 = Disable interrupt generation\r
-\r
- Store(0x54,HCON)\r
-\r
- // Step 3: Wait up to 200ms to get the Data Count.\r
-\r
- Store(4000,Local0) // 4000 * 50us = 200ms.\r
-\r
- While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
- {\r
- Decrement(Local0) // Decrement Count.\r
- Stall(50) // Delay = 50us.\r
- }\r
-\r
- If(LNot(Local0)) // Timeout?\r
- {\r
- KILL() // Yes. Kill Communication.\r
- Return(0) // Return failure.\r
- }\r
-\r
- Store(DAT0,Index(TBUF,0)) // Get the Data Count.\r
- Store(0x80,HSTS) // Clear Host Status.\r
- Store(1,Local1) // Local1 = Buffer Pointer.\r
-\r
- // Step 4: Get the Block Data and store it.\r
-\r
- While(LLess(Local1,DerefOf(Index(TBUF,0))))\r
- {\r
- // Wait up to 200ms for Host Status to get set.\r
-\r
- Store(4000,Local0) // 4000 * 50us = 200ms.\r
-\r
- While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
- {\r
- Decrement(Local0) // Decrement Count.\r
- Stall(50) // Delay = 50us.\r
- }\r
-\r
- If(LNot(Local0)) // Timeout?\r
- {\r
- KILL() // Yes. Kill Communication.\r
- Return(0) // Return failure.\r
- }\r
-\r
- Store(HBDR,Index(TBUF,Local1)) // Place into Buffer.\r
- Store(0x80,HSTS) // Clear Host Status.\r
- Increment(Local1)\r
- }\r
-\r
- // Step 5: Exit the Method correctly.\r
-\r
- If(COMP())\r
- {\r
- Or(HSTS,0xFF,HSTS) // Clear INUSE_STS and others.\r
- Return(TBUF) // Return Success.\r
- }\r
-\r
- Return(0) // Return Failure.\r
-}\r
-\r
-\r
-// SMBus Start Check\r
-// Return: Success = 0\r
-// Failure = 1\r
-\r
-Method(STRT,0,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Wait up to 200ms to confirm the SMBus Semaphore has been\r
- // released (In Use Status = 0). Note that the Sleep time may take\r
- // longer as the This function will yield the Processor such that it\r
- // may perform different tasks during the delay.\r
-\r
- Store(200,Local0) // 200 * 1ms = 200ms.\r
-\r
- While(Local0)\r
- {\r
- If(And(HSTS,0x40)) // In Use Set?\r
- {\r
- Decrement(Local0) // Yes. Decrement Count.\r
- Sleep(1) // Delay = 1ms.\r
- If(LEqual(Local0,0)) // Count = 0?\r
- {\r
- Return(1) // Return failure.\r
- }\r
- }\r
- Else\r
- {\r
- Store(0,Local0) // In Use Clear. Continue.\r
- }\r
- }\r
-\r
- // In Use Status = 0 during last read, which will make subsequent\r
- // reads return In Use Status = 1 until software clears it. All\r
- // software using ICHx SMBus should check this bit before initiating\r
- // any SMBus communication.\r
-\r
- // Wait up to 200ms to confirm the Host Interface is\r
- // not processing a command.\r
-\r
- Store(4000,Local0) // 4000 * 50us = 200ms.\r
-\r
- While(Local0)\r
- {\r
- If(And(HSTS,0x01)) // Host Busy Set?\r
- {\r
- Decrement(Local0) // Decrement Count.\r
- Stall(50) // Delay = 50us.\r
- If(LEqual(Local0,0)) // Count = 0?\r
- {\r
- KILL() // Yes. Kill Communication.\r
- }\r
- }\r
- Else\r
- {\r
- Return(0)\r
- }\r
- }\r
-\r
- Return(1) // Timeout. Return failure.\r
-}\r
-\r
-// SMBus Completion Check\r
-// Return: Success = 1\r
-// Failure = 0\r
-\r
-Method(COMP,0,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- // Wait for up to 200ms for the Completion Command\r
- // Status to get set.\r
-\r
- Store(4000,Local0) // 4000 * 50us = 200ms.\r
-\r
- While(Local0)\r
- {\r
- If(And(HSTS,0x02)) // Completion Status Set?\r
- {\r
- Return(1) // Yes. We are done.\r
- }\r
- Else\r
- {\r
- Decrement(Local0) // Decrement Count.\r
- Stall(50) // Delay 50us.\r
- If(LEqual(Local0,0)) // Count = 0?\r
- {\r
- KILL() // Yes. Kill Communication.\r
- }\r
- }\r
- }\r
-\r
- Return(0) // Timeout. Return Failure.\r
-}\r
-\r
-// SMBus Kill Command\r
-\r
-Method(KILL,0,Serialized)\r
-{\r
- OperationRegion(SMPB,PCI_Config,0x20,4)\r
- Field(SMPB,DWordAcc,NoLock,Preserve)\r
- {\r
- , 5,\r
- SBAR, 11\r
- }\r
-\r
- // Define various SMBus IO Mapped Registers.\r
-\r
- OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
- Field(SMBI,ByteAcc,NoLock,Preserve)\r
- {\r
- HSTS, 8, // 0 - Host Status Register\r
- Offset(0x02),\r
- HCON, 8, // 2 - Host Control\r
- HCOM, 8, // 3 - Host Command\r
- TXSA, 8, // 4 - Transmit Slave Address\r
- DAT0, 8, // 5 - Host Data 0\r
- DAT1, 8, // 6 - Host Data 1\r
- HBDR, 8, // 7 - Host Block Data\r
- PECR, 8, // 8 - Packer Error Check\r
- RXSA, 8, // 9 - Receive Slave Address\r
- SDAT, 16, // A - Slave Data\r
- }\r
- Or(HCON,0x02,HCON) // Yes. Send Kill command.\r
- Or(HSTS,0xFF,HSTS) // Clear all status.\r
-}\r
projects / mirror_edk2.git / blobdiff