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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / Include / Ppi / VlvPolicy.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h
new file mode 100644 (file)
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+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h
@@ -0,0 +1,110 @@
+\r
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between ValleyView MRC and platform drivers during PEI phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_POLICY_PPI_H_\r
+#define _VLV_POLICY_PPI_H_\r
+\r
+//\r
+// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}\r
+//\r
+#define VLV_POLICY_PPI_GUID \\r
+  { \\r
+    0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \\r
+  }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gVlvPolicyPpiGuid;\r
+\r
+//\r
+// PPI revision number\r
+// Any backwards compatible changes to this PPI will result in an update in the revision number\r
+// Major changes will require publication of a new PPI\r
+//\r
+#define MRC_PLATFORM_POLICY_PPI_REVISION  1\r
+\r
+#ifndef MAX_SOCKETS\r
+#define MAX_SOCKETS 4\r
+#endif\r
+\r
+#define S3_TIMING_DATA_LEN          9\r
+#define S3_READ_TRAINING_DATA_LEN   16\r
+#define S3_WRITE_TRAINING_DATA_LEN  12\r
+\r
+#ifndef S3_RESTORE_DATA_LEN\r
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)\r
+#endif // S3_RESTORE_DATA_LEN\r
+#pragma pack(1)\r
+//\r
+// MRC Platform Data Structure\r
+//\r
+typedef struct {\r
+  UINT8   SpdAddressTable[MAX_SOCKETS];\r
+  UINT8   TSonDimmSmbusAddress[MAX_SOCKETS];\r
+\r
+  UINT16  SmbusBar;\r
+  UINT32  IchRcba;\r
+  UINT32  WdbBaseAddress; // Write Data Buffer area (WC caching mode)\r
+  UINT32  WdbRegionSize;\r
+  UINT32  SmBusAddress;\r
+  UINT8   UserBd;\r
+  UINT8   PlatformType;\r
+  UINT8   FastBoot;\r
+  UINT8   DynSR;\r
+} VLV_PLATFORM_DATA;\r
+\r
+\r
+typedef struct {\r
+  UINT16  MmioSize;\r
+  UINT16  GttSize;\r
+  UINT8   IgdDvmt50PreAlloc;\r
+  UINT8   PrimaryDisplay;\r
+  UINT8   PAVPMode;\r
+  UINT8   ApertureSize;\r
+} GT_CONFIGURATION;\r
+\r
+typedef struct {\r
+  UINT8   EccSupport;\r
+  UINT16  DdrFreqLimit;\r
+  UINT8   MaxTolud;\r
+} MEMORY_CONFIGURATION;\r
+\r
+\r
+//\r
+// MRC Platform Policiy PPI\r
+//\r
+typedef struct _VLV_POLICY_PPI {\r
+  UINT8                 Revision;\r
+  VLV_PLATFORM_DATA     PlatformData;\r
+  GT_CONFIGURATION      GtConfig;\r
+  MEMORY_CONFIGURATION  MemConfig;\r
+  VOID                  *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE\r
+  UINT8                 ISPEn;            //ISP (IUNIT) Device Enabled\r
+  UINT8                 ISPPciDevConfig;  //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS\r
+} VLV_POLICY_PPI;\r
+\r
+#pragma pack()\r
+\r
+#endif // _VLV_POLICY_PPI_H_\r