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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / CPU / Include / Protocol / PpmPlatformPolicy.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h
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+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h
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+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+/*++\r
+\r
+Module Name:\r
+\r
+  PpmPlatformPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between PPM and platform drivers during DXE phase.\r
+\r
+--*/\r
+#ifndef _PPM_PLATFORM_POLICY_H_\r
+#define _PPM_PLATFORM_POLICY_H_\r
+\r
+//\r
+//  PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}\r
+//\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_GUID \\r
+  {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gPpmPlatformPolicyProtocolGuid;\r
+\r
+//\r
+// Forward reference for ANSI C compatibility\r
+//\r
+typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;\r
+\r
+//\r
+// Protocol revision number\r
+// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+// Major changes will require publication of a new protocol\r
+//\r
+// Revision 1: Original version\r
+// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable\r
+// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)\r
+// Revision 4: Added support for extended C6 residency enabling\r
+//\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION     1\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2   2\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3   3\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4   4\r
+\r
+//\r
+// Define maximum number of custom VID states supported\r
+//\r
+#ifndef MAX_CUSTOM_VID_TABLE_STATES\r
+#define MAX_CUSTOM_VID_TABLE_STATES               6\r
+#endif\r
+//\r
+// Custom VID table\r
+//\r
+typedef struct {\r
+  UINT8   VidNumber;\r
+  UINT32  VidCpuid;\r
+  UINT16  VidMaxRatio;\r
+  UINT16  VidMaxVid;\r
+  UINT16  StateRatio[MAX_CUSTOM_VID_TABLE_STATES];\r
+  UINT16  StateVid[MAX_CUSTOM_VID_TABLE_STATES];\r
+} PPM_CUSTOM_VID_TABLE;\r
+\r
+//\r
+// PPM functional enables\r
+//\r
+typedef struct {\r
+  UINT8   EnableGv                   :1; // 0: Disabled; 1: Enabled\r
+  UINT8   EnableCx                   :1;\r
+  UINT8   EnableCxe                  :1;\r
+  UINT8   EnableC4                   :1;\r
+  UINT8   EnableC6                   :1;\r
+  UINT8   EnableC7                   :1;\r
+  UINT8   EnableTm                   :1;\r
+  UINT8   Reserve00                  :1;\r
+  UINT8   Reserve01                  :1;\r
+  UINT8   EnableTurboMode            :1;\r
+  UINT8   PowerLimit2                :1;\r
+  UINT8   EnableProcHot              :1;\r
+  UINT8   Reserve02                  :1;\r
+  UINT8   EnableCMP                  :1;\r
+  UINT8   TStatesEnable              :1;\r
+  UINT8   Reserve03                  :1;\r
+  UINT8   Reserve04                  ;\r
+\r
+} PPM_FUNCTION_ENABLES;\r
+\r
+\r
+//\r
+// PPM Turbo settings\r
+//\r
+typedef struct _PPM_TURBO_SETTINGS {\r
+  UINT16  PowerLimit1;\r
+  UINT32  PowerLimit1Time;\r
+  UINT16  PowerLimit2;\r
+  UINT8   TurboPowerLimitLock;\r
+} PPM_TURBO_SETTINGS;\r
+\r
+//\r
+// Platform Policy\r
+//\r
+typedef struct _PPM_PLATFORM_POLICY_PROTOCOL {\r
+  UINT8                                 Revision;\r
+  PPM_FUNCTION_ENABLES                  FunctionEnables;\r
+  PPM_CUSTOM_VID_TABLE                  CustomVidTable;\r
+  PPM_TURBO_SETTINGS                    TurboSettings;\r
+\r
+  UINT8                                 Reserve00;\r
+  UINT8                                 Reserve01;\r
+  UINT8                                 Reserve02;\r
+  UINT8                                 Reserve03;\r
+  UINT8                                 Reserve04;\r
+  UINT8                                 Reserve05;\r
+  UINT8                                 Reserve06;\r
+\r
+  UINT8                                 S3RestoreMsrSwSmiNumber;\r
+  UINT8                                 Reserve07;\r
+  UINT32                                Reserve08;\r
+  UINT8                                 Reserve09;\r
+  //\r
+  // Primary and Secondary Plane Current Limits\r
+  //\r
+  UINT16                                Reserve10;\r
+  UINT8                                 Reserve11;\r
+} PPM_PLATFORM_POLICY_PROTOCOL;\r
+\r
+#endif\r