+++ /dev/null
-/*-----------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
-\r
-\r
- Intel Platform Processor Power Management BIOS Reference Code\r
-\r
- Copyright (c) 2007 - 2014, Intel Corporation\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
- Filename: APTST.ASL\r
-\r
- Revision: Refer to Readme\r
-\r
- Date: Refer to Readme\r
-\r
---------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
-\r
- This Processor Power Management BIOS Source Code is furnished under license\r
- and may only be used or copied in accordance with the terms of the license.\r
- The information in this document is furnished for informational use only, is\r
- subject to change without notice, and should not be construed as a commitment\r
- by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
- for any errors or inaccuracies that may appear in this document or any\r
- software that may be provided in association with this document.\r
-\r
- Except as permitted by such license, no part of this document may be\r
- reproduced, stored in a retrieval system, or transmitted in any form or by\r
- any means without the express written consent of Intel Corporation.\r
-\r
- WARNING: You are authorized and licensed to install and use this BIOS code\r
- ONLY on an IST PC. This utility may damage any system that does not\r
- meet these requirements.\r
-\r
- An IST PC is a computer which\r
- (1) Is capable of seamlessly and automatically transitioning among\r
- multiple performance states (potentially operating at different\r
- efficiency ratings) based upon power source changes, END user\r
- preference, processor performance demand, and thermal conditions; and\r
- (2) Includes an Intel Pentium II processors, Intel Pentium III\r
- processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
- Processor-M, Intel Pentium M Processor, or any other future Intel\r
- processors that incorporates the capability to transition between\r
- different performance states by altering some, or any combination of,\r
- the following processor attributes: core voltage, core frequency, bus\r
- frequency, number of processor cores available, or any other attribute\r
- that changes the efficiency (instructions/unit time-power) at which the\r
- processor operates.\r
-\r
--------------------------------------------------------------------------------\r
--------------------------------------------------------------------------------\r
-\r
-NOTES:\r
- (1) <TODO> - IF the trap range and port definitions do not match those\r
- specified by this reference code, this file must be modified IAW the\r
- individual implmentation.\r
-\r
---------------------------------------------------------------------------------\r
-------------------------------------------------------------------------------*/\r
-\r
-\r
-DefinitionBlock(\r
- "APTST.aml",\r
- "SSDT",\r
- 0x01,\r
- "PmRef",\r
- "ApTst",\r
- 0x3000\r
- )\r
-{\r
- External(\_PR.CPU1, DeviceObj)\r
- External(\_PR.CPU2, DeviceObj)\r
- External(\_PR.CPU3, DeviceObj)\r
- External(\_PR.CPU0._PTC)\r
- External(\_PR.CPU0._TSS)\r
- External(PDC0)\r
- External(CFGD)\r
- External(MPEN)\r
-\r
- Scope(\_PR.CPU1)\r
- {\r
- Name(_TPC, 0) // All T-States are available\r
-\r
- //\r
- // T-State Control/Status interface\r
- //\r
- Method(_PTC, 0)\r
- {\r
- Return(\_PR.CPU0._PTC)\r
- }\r
-\r
- Method(_TSS, 0)\r
- {\r
- Return(\_PR.CPU0._TSS)\r
- }\r
-\r
- //\r
- // T-State Dependency\r
- //\r
- Method(_TSD, 0)\r
- {\r
- //\r
- // IF four cores are supported/enabled && !(direct access to MSR)\r
- // Report 4 processors and SW_ANY as the coordination\r
- // IF two cores are supported/enabled && !(direct access to MSR)\r
- // Report 2 processors and SW_ANY as the coordination type\r
- // ELSE\r
- // Report 1 processor and SW_ALL as the coordination type (domain 1)\r
- //\r
- // CFGD[23] = Four cores enabled\r
- // CFGD[24] = Two or more cores enabled\r
- // PDCx[2] = OSPM is capable of direct access to On\r
- // Demand throttling MSR\r
- //\r
-\r
- If(LNot(And(PDC0,4)))\r
- {\r
- Return(Package(){ // SW_ANY\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 0, // Domain #.\r
- 0xFD, // Coord Type- SW_ANY\r
- MPEN // # processors.\r
- }\r
- })\r
- }\r
- Return(Package(){ // SW_ALL\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 1, // Domain #.\r
- 0xFC, // Coord Type- SW_ALL\r
- 1 // # processors.\r
- }\r
- })\r
- }\r
- } // End of CPU1\r
-\r
- Scope(\_PR.CPU2)\r
- {\r
- Name(_TPC, 0) // All T-States are available\r
-\r
- //\r
- // T-State Control/Status interface\r
- //\r
- Method(_PTC, 0)\r
- {\r
- Return(\_PR.CPU0._PTC)\r
- }\r
-\r
- Method(_TSS, 0)\r
- {\r
- Return(\_PR.CPU0._TSS)\r
- }\r
-\r
- //\r
- // T-State Dependency\r
- //\r
- Method(_TSD, 0)\r
- {\r
- //\r
- // IF four cores are supported/enabled && !(direct access to MSR)\r
- // Report 4 processors and SW_ANY as the coordination\r
- // IF two cores are supported/enabled && !(direct access to MSR)\r
- // Report 2 processors and SW_ANY as the coordination type\r
- // ELSE\r
- // Report 1 processor and SW_ALL as the coordination type (domain 1)\r
- //\r
- // CFGD[23] = Four cores enabled\r
- // CFGD[24] = Two or more cores enabled\r
- // PDCx[2] = OSPM is capable of direct access to On\r
- // Demand throttling MSR\r
- //\r
-\r
- If(LNot(And(PDC0,4)))\r
- {\r
- Return(Package(){ // SW_ANY\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 0, // Domain #.\r
- 0xFD, // Coord Type- SW_ANY\r
- MPEN // # processors.\r
- }\r
- })\r
- }\r
- Return(Package(){ // SW_ALL\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 1, // Domain #.\r
- 0xFC, // Coord Type- SW_ALL\r
- 1 // # processors.\r
- }\r
- })\r
- }\r
- } // End of CPU2\r
-\r
- Scope(\_PR.CPU3)\r
- {\r
- Name(_TPC, 0) // All T-States are available\r
-\r
- //\r
- // T-State Control/Status interface\r
- //\r
- Method(_PTC, 0)\r
- {\r
- Return(\_PR.CPU0._PTC)\r
- }\r
-\r
- Method(_TSS, 0)\r
- {\r
- Return(\_PR.CPU0._TSS)\r
- }\r
-\r
- //\r
- // T-State Dependency\r
- //\r
- Method(_TSD, 0)\r
- {\r
- //\r
- // IF four cores are supported/enabled && !(direct access to MSR)\r
- // Report 4 processors and SW_ANY as the coordination\r
- // IF two cores are supported/enabled && !(direct access to MSR)\r
- // Report 2 processors and SW_ANY as the coordination type\r
- // ELSE\r
- // Report 1 processor and SW_ALL as the coordination type (domain 1)\r
- //\r
- // CFGD[23] = Four cores enabled\r
- // CFGD[24] = Two or more cores enabled\r
- // PDCx[2] = OSPM is capable of direct access to On\r
- // Demand throttling MSR\r
- //\r
-\r
- If(LNot(And(PDC0,4)))\r
- {\r
- Return(Package(){ // SW_ANY\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 0, // Domain #.\r
- 0xFD, // Coord Type- SW_ANY\r
- MPEN // # processors.\r
- }\r
- })\r
- }\r
- Return(Package(){ // SW_ALL\r
- Package(){\r
- 5, // # entries.\r
- 0, // Revision.\r
- 1, // Domain #.\r
- 0xFC, // Coord Type- SW_ALL\r
- 1 // # processors.\r
- }\r
- })\r
- }\r
- } // End of CPU3\r
-} // End of Definition Block\r
-\r
projects / mirror_edk2.git / blobdiff