--- /dev/null
+\r
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename: CPU0CST.ASL\r
+\r
+ Revision: Refer to Readme\r
+\r
+ Date: Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+ An IST PC is a computer which\r
+ (1) Is capable of seamlessly and automatically transitioning among\r
+ multiple performance states (potentially operating at different\r
+ efficiency ratings) based upon power source changes, END user\r
+ preference, processor performance demand, and thermal conditions; and\r
+ (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+ processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+ Processor-M, Intel Pentium M Processor, or any other future Intel\r
+ processors that incorporates the capability to transition between\r
+ different performance states by altering some, or any combination of,\r
+ the following processor attributes: core voltage, core frequency, bus\r
+ frequency, number of processor cores available, or any other attribute\r
+ that changes the efficiency (instructions/unit time-power) at which the\r
+ processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+ (1) <TODO> - IF the trap range and port definitions do not match those\r
+ specified by this reference code, this file must be modified IAW the\r
+ individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+ "CPU0CST.aml",\r
+ "SSDT",\r
+ 1,\r
+ "PmRef",\r
+ "Cpu0Cst",\r
+ 0x3001\r
+ )\r
+{\r
+ External(\_PR.CPU0, DeviceObj)\r
+ External(PWRS)\r
+ External(CFGD)\r
+ External(PDC0)\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG\r
+ Field (DEB0, ByteAcc,NoLock,Preserve) //DBG\r
+ { DBG8, 8,} //DBG\r
+\r
+ Method (_CST, 0)\r
+ {\r
+ Store(0x60,DBG8) //DBG\r
+\r
+ // IF CMP is supported, but independent C-States beyond C1 are\r
+ // not supported; return C1 Halt and rely on BIOS based software\r
+ // coordination\r
+ //\r
+ // CFGD[24] = CMP support\r
+ // PDCx[4] = 0 - OS does not support ind. C2/C3 in MP systems\r
+ //\r
+ // Note: SMI will be generated when both processor enter the\r
+ // Halt state.\r
+ //\r
+ If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
+ {\r
+ Store(0x61,DBG8) //DBG\r
+ Return(Package() {\r
+ 1,\r
+ Package()\r
+ { // C1 halt, but with BIOS coordination\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 157,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+\r
+ // IF MWAIT extensions are supported, use them.\r
+ //\r
+ // IF C6 capable/enabled AND Battery\r
+ // Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
+ // ELSE IF C4 capable/enabled AND Battery\r
+ // Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
+ // ELSE IF C3 capable/enabled\r
+ // Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
+ // ELSE IF C2 capable/enabled\r
+ // Report MWAIT C1, C2\r
+ // ELSE\r
+ // Report MWAIT C1\r
+ //\r
+ // CFGD[21] = 1 - MWAIT extensions supported\r
+ // CFGD[13] = 1 - C7 Capable/Enabled\r
+ // CFGD[12] = 1 - C6S Capable/Enabled\r
+ // CFGD[11] = 1 - C6 Capable/Enabled\r
+ // CFGD[7] = 1 - C4 Capable/Enabled\r
+ // CFGD[5] = 1 - C3 Capable/Enabled\r
+ // PDCx[9] = 1 - OS supports MWAIT extensions\r
+ // PDCx[8] = 1 - OS supports MWAIT for C1\r
+ // (Inferred from PDCx[9] = 1.)\r
+ // PDCx[4] = 1 - OS supports independent C2/C3 in MP systems\r
+ // or\r
+ // NOT CMP (Inferred from previous check.)\r
+ //\r
+ If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
+ {\r
+ //\r
+ // <TODO> The implementor may wish to only report C1-C2\r
+ // when on AC power. In this case, the IF clause below can\r
+ // be modified to something like:\r
+ //\r
+ // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
+ //\r
+ // Which uses the power state of the system (PWRS) to\r
+ // determine whether to allow deepers states.\r
+ //\r
+ // IF C7 supported AND on battery\r
+ // report MWAIT C1, C6, C7\r
+ //\r
+ // CFGD[13] = C7 Capable/Enabled\r
+ // CFGD[11] = C6 Capable/Enabled\r
+ //\r
+ If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
+ {\r
+ Store(0x77,DBG8) //DBG\r
+ Return( Package()\r
+ {\r
+ 3,\r
+ Package()\r
+ { // C1, MWAIT\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ {\r
+ // C6, MWAIT Extension with Incremental L2 Shrink\r
+ // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+ // C6, MWAIT Extension with No L2 Shrink\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+ 2,\r
+ 500,\r
+ 10\r
+ },\r
+ Package()\r
+ {\r
+ // C7, MWAIT Extension with Full L2 Shrink\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
+ 3,\r
+ 1500, //PnP setting, 1.5 ms for worst-case exit latency\r
+ 10\r
+ }\r
+ })\r
+ }\r
+\r
+\r
+ If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
+ {\r
+ Store(0x67,DBG8) //DBG\r
+ Return( Package()\r
+ {\r
+ 3,\r
+ Package()\r
+ { // C1, MWAIT\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ {\r
+ // C6, MWAIT Extension with Incremental L2 Shrink\r
+ // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+ // C6 = C6NS, MWAIT Extension with No L2 Shrink\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+ 2,\r
+ 500,\r
+ 10\r
+ },\r
+ Package()\r
+ {\r
+\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
+ 3,\r
+ 1500, //PnP setting, 1.5 ms for worst-case exit latency\r
+ 10\r
+ }\r
+ })\r
+ }\r
+\r
+ If(And(CFGD,0x800)) // Setup Max C-State = C6\r
+ {\r
+ Store(0x76,DBG8) //DBG\r
+ Return( Package()\r
+ {\r
+ 2,\r
+ Package()\r
+ { // C1, MWAIT\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ {\r
+ // C6, MWAIT Extension with Incremental L2 Shrink\r
+ // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+ // C6, MWAIT Extension with No L2 Shrink\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+ 2,\r
+ 500,\r
+ 10\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // IF no deeper C-States are supported; report MWAIT C1.\r
+ //\r
+ Store(0x71,DBG8) //DBG\r
+ Return(Package()\r
+ {\r
+ 1,\r
+ Package()\r
+ { // C1, MWAIT\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+\r
+\r
+ }\r
+ }\r
+}\r
+\r
+\r
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