--- /dev/null
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename: CPU0IST.ASL\r
+\r
+ Revision: Refer to Readme\r
+\r
+ Date: Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+ An IST PC is a computer which\r
+ (1) Is capable of seamlessly and automatically transitioning among\r
+ multiple performance states (potentially operating at different\r
+ efficiency ratings) based upon power source changes, END user\r
+ preference, processor performance demand, and thermal conditions; and\r
+ (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+ processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+ Processor-M, Intel Pentium M Processor, or any other future Intel\r
+ processors that incorporates the capability to transition between\r
+ different performance states by altering some, or any combination of,\r
+ the following processor attributes: core voltage, core frequency, bus\r
+ frequency, number of processor cores available, or any other attribute\r
+ that changes the efficiency (instructions/unit time-power) at which the\r
+ processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+ (1) <TODO> - IF the trap range and port definitions do not match those\r
+ specified by this reference code, this file must be modified IAW the\r
+ individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+ "CPU0IST.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "PmRef",\r
+ "Cpu0Ist",\r
+ 0x3000\r
+ )\r
+{\r
+ External (\_PR.CPU0, DeviceObj)\r
+ External (PDC0)\r
+ External (CFGD)\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ //OperationRegion (DEB0, SystemIO, 0x80, 1) //DBG\r
+ //Field (DEB0, ByteAcc,NoLock,Preserve) //DBG\r
+ //{ DBG8, 8,} //DBG\r
+\r
+ Name(_PPC, 0) // Initialize as All States Available.\r
+\r
+ // NOTE: For CMP systems; this table is not loaded unless\r
+ // the required driver support is present.\r
+ // So, we do not check for those cases here.\r
+ //\r
+ // CFGD[0] = GV3 Capable/Enabled\r
+ // PDCx[0] = OS Capable of Hardware P-State control\r
+ //\r
+ Method(_PCT,0)\r
+ {\r
+ If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
+ {\r
+ //Store(0xA0,DBG8) //DBG\r
+ Return(Package() // Native Mode\r
+ {\r
+ ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
+ ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
+ })\r
+ }\r
+ // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT\r
+ // For all other cases, report control through the\r
+ // SMI interface. (The port used for SMM control is fixed up\r
+ // by the initialization code.)\r
+ //\r
+ Return(Package() // SMM Mode\r
+ {\r
+ ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
+ ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
+ })\r
+ }\r
+\r
+\r
+ // NOTE: For CMP systems; this table is not loaded if MP\r
+ // driver support is not present or P-State are disabled.\r
+ //\r
+ Method(_PSS,0)\r
+ {\r
+ //\r
+ // Report NSPP if:\r
+ // (1) GV3 capable (Not checked, see above.)\r
+ // (2) Driver support direct hardware control\r
+ // (3) MP driver support present (Not checked, see above.)\r
+ // else;\r
+ // Report SPSS\r
+ //\r
+ // PDCx[0] = OS Capable of Hardware P-State control\r
+ //\r
+ If(And(PDC0,0x0001)){\r
+ //Store(0xB0,DBG8) //DBG\r
+ Return(NPSS)\r
+ }\r
+ //Store(0xBF,DBG8) //DBG\r
+ // Otherwise, report SMM mode\r
+ //\r
+ Return(SPSS)\r
+\r
+ }\r
+\r
+ Name(SPSS,Package()\r
+ {\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+ })\r
+\r
+ Name(NPSS,Package()\r
+ {\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+ })\r
+\r
+ // The _PSD object provides information to the OSPM related\r
+ // to P-State coordination between processors in a multi-processor\r
+ // configurations.\r
+ //\r
+ Method(_PSD,0)\r
+ {\r
+ //\r
+ // IF CMP is supported/enabled\r
+ // IF quad core processor\r
+ // IF PDC[11]\r
+ // Report 4 processors and HW_ALL as the coordination type\r
+ // ELSE\r
+ // Report 4 processors and SW_ALL as the coordination type\r
+ // ELSE\r
+ // IF PDC[11]\r
+ // Report 2 processors and HW_ALL as the coordination type\r
+ // ELSE\r
+ // Report 2 processors and SW_ALL as the coordination type\r
+ // ELSE\r
+ // Report 1 processor and SW_ALL as the coordination type\r
+ // (Domain 0)\r
+ //\r
+ // CFGD[24] = Two or more cores enabled\r
+ // CFGD[23] = Four cores enabled\r
+ // PDCx[11] = Hardware coordination with hardware feedback\r
+ //\r
+\r
+ If(And(CFGD,0x1000000)) // CMP Enabled.\r
+ {\r
+ If(And(CFGD,0x800000)) // 2 or 4 process.\r
+ {\r
+ If(And(PDC0,0x0800))\r
+ {\r
+ Return(Package(){ // HW_ALL\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFE, // Coord Type- HW_ALL.\r
+ 4 // # processors.\r
+ }\r
+ })\r
+ } // If(And(PDC0,0x0800))\r
+ Return(Package(){ // SW_ALL\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFC, // Coord Type- SW_ALL.\r
+ 4 // # processors.\r
+ }\r
+ })\r
+ } else {\r
+ Return(Package(){ // HW_ALL\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFE, // Coord Type- HW_ALL.\r
+ 2 // # processors.\r
+ }\r
+ })\r
+ }\r
+ } // If(And(CFGD,0x1000000)) // CMP Enabled.\r
+\r
+ Return(Package(){ // SW_ALL\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFC, // Coord Type- SW_ALL.\r
+ 1 // # processors.\r
+ }\r
+ })\r
+ } // Method(_PSD,0)\r
+ } // Scope(\_PR.CPU0)\r
+} // End of Definition Block\r
+\r
+\r
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