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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / NorthCluster / Include / Ppi / PlatformMemoryRange.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h
new file mode 100644 (file)
index 0000000..b2faf4c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h
@@ -0,0 +1,150 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformMemoryRange.h\r
+\r
+Abstract:\r
+\r
+  Platform Memory Range PPI as defined in EFI 2.0\r
+\r
+  PPI for reserving special purpose memory ranges.\r
+\r
+--*/\r
+//\r
+//\r
+#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_\r
+#define _PEI_PLATFORM_MEMORY_RANGE_H_\r
+\r
+#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \\r
+  { \\r
+    0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \\r
+  }\r
+\r
+typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI  PEI_PLATFORM_MEMORY_RANGE_PPI ;\r
+\r
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
+\r
+#define PEI_MR_OPTION_ROM_ALL       0xFFFFFFFF\r
+#define PEI_MR_OPTION_ROM_NONE      0x00000000\r
+#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001\r
+#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002\r
+#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004\r
+#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008\r
+#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010\r
+#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020\r
+#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040\r
+#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080\r
+#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100\r
+#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200\r
+#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400\r
+#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800\r
+#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000\r
+#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000\r
+#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000\r
+#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000\r
+\r
+//\r
+// SMRAM Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_SMRAM      UINT32\r
+#define PEI_MR_SMRAM_ALL            0xFFFFFFFF\r
+#define PEI_MR_SMRAM_NONE           0x00000000\r
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
+#define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000\r
+#define PEI_MR_SMRAM_ABSEG_MASK     0x00010000\r
+#define PEI_MR_SMRAM_HSEG_MASK      0x00020000\r
+#define PEI_MR_SMRAM_TSEG_MASK      0x00040000\r
+//\r
+// If adding additional entries, SMRAM Size\r
+// is a multiple of 128KB.\r
+//\r
+#define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF\r
+#define PEI_MR_SMRAM_SIZE_128K_MASK     0x00000001\r
+#define PEI_MR_SMRAM_SIZE_256K_MASK     0x00000002\r
+#define PEI_MR_SMRAM_SIZE_512K_MASK     0x00000004\r
+#define PEI_MR_SMRAM_SIZE_1024K_MASK    0x00000008\r
+#define PEI_MR_SMRAM_SIZE_2048K_MASK    0x00000010\r
+#define PEI_MR_SMRAM_SIZE_4096K_MASK    0x00000020\r
+#define PEI_MR_SMRAM_SIZE_8192K_MASK    0x00000040\r
+\r
+#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001\r
+#define PEI_MR_SMRAM_HSEG_128K_CACHE    0x80020001\r
+#define PEI_MR_SMRAM_HSEG_128K_NOCACHE  0x00020001\r
+#define PEI_MR_SMRAM_TSEG_128K_CACHE    0x80040001\r
+#define PEI_MR_SMRAM_TSEG_128K_NOCACHE  0x00040001\r
+#define PEI_MR_SMRAM_TSEG_256K_CACHE    0x80040002\r
+#define PEI_MR_SMRAM_TSEG_256K_NOCACHE  0x00040002\r
+#define PEI_MR_SMRAM_TSEG_512K_CACHE    0x80040004\r
+#define PEI_MR_SMRAM_TSEG_512K_NOCACHE  0x00040004\r
+#define PEI_MR_SMRAM_TSEG_1024K_CACHE   0x80040008\r
+#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008\r
+\r
+//\r
+// Graphics Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY  UINT32\r
+#define PEI_MR_GRAPHICS_MEMORY_ALL        0xFFFFFFFF\r
+#define PEI_MR_GRAPHICS_MEMORY_NONE       0x00000000\r
+#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE  0x80000000\r
+//\r
+// If adding additional entries, Graphics Memory Size\r
+// is a multiple of 512KB.\r
+//\r
+#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK    0x0000FFFF\r
+#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001\r
+#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE   0x80000001\r
+#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE   0x00000002\r
+#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE     0x80000002\r
+#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE   0x00000008\r
+#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE     0x80000008\r
+#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE   0x00000010\r
+#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE     0x80000010\r
+#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE  0x00000020\r
+#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE    0x80000020\r
+#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE  0x00000040\r
+#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE    0x80000040\r
+#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE  0x00000060\r
+#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE    0x80000060\r
+#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE  0x00000080\r
+#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE    0x80000080\r
+#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100\r
+#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE   0x80000100\r
+#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200\r
+#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE   0x80000200\r
+//\r
+// Pci Memory Hole\r
+//\r
+#define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32\r
+#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK  0x00000001\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_CHOOSE_RANGES) (\r
+  IN      EFI_PEI_SERVICES                      **PeiServices,\r
+  IN PEI_PLATFORM_MEMORY_RANGE_PPI              * This,\r
+  IN OUT  PEI_MEMORY_RANGE_OPTION_ROM           * OptionRomMask,\r
+  IN OUT  PEI_MEMORY_RANGE_SMRAM                * SmramMask,\r
+  IN OUT  PEI_MEMORY_RANGE_GRAPHICS_MEMORY      * GraphicsMemoryMask,\r
+  IN OUT  PEI_MEMORY_RANGE_PCI_MEMORY           * PciMemoryMask\r
+  );\r
+\r
+struct _PEI_PLATFORM_MEMORY_RANGE_PPI {\r
+  PEI_CHOOSE_RANGES ChooseRanges;\r
+};\r
+\r
+extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;\r
+\r
+#endif\r