+++ /dev/null
-\r
-/*++\r
-\r
-Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-\r
-Module Name:\r
-\r
- Valleyview.h\r
-\r
-Abstract:\r
-\r
- This header file provides common definitions just for Valleyview-SOC using to avoid including extra module's file.\r
---*/\r
-\r
-#ifndef _MC_H_INCLUDED_\r
-#define _MC_H_INCLUDED_\r
-/*\r
-< Extended Configuration Base Address.*/\r
-#define EC_BASE 0xE0000000\r
-\r
-//\r
-// DEVICE 0 (Memroy Controller Hub)\r
-//\r
-#define MC_BUS 0x00\r
-#define MC_DEV 0x00\r
-#define MC_DEV2 0x02\r
-#define MC_FUN 0x00\r
-// NC DEV 0 Vendor and Device IDs\r
-#define MC_VID 0x8086\r
-#define MC_DID_OFFSET 0x2 //Device Identification\r
-#define MC_GGC_OFFSET 0x50 //GMCH Graphics Control Register\r
-\r
-//\r
-// Device 2 Register Equates\r
-//\r
-#define IGD_BUS 0x00\r
-#define IGD_DEV 0x02\r
-#define IGD_FUN_0 0x00\r
-#define IGD_FUN_1 0x01\r
-#define IGD_DEV_FUN (IGD_DEV << 3)\r
-#define IGD_BUS_DEV_FUN (MC_BUS << 8) + IGD_DEV_FUN\r
-#define IGD_VID 0x8086\r
-#define IGD_DID 0xA001\r
-#define IGD_MGGC_OFFSET 0x0050 //GMCH Graphics Control Register 0x50\r
-#define IGD_BSM_OFFSET 0x005C //Base of Stolen Memory\r
-#define IGD_SWSCI_OFFSET 0x00E0 //Software SCI 0xE0 2\r
-#define IGD_ASLE_OFFSET 0x00E4 //System Display Event Register 0xE4 4\r
-#define IGD_ASLS_OFFSET 0x00FC // ASL Storage\r
-#define IGD_DID_QS 0x0BE2 //RCOverride -a: Fix the DID error\r
-\r
-#endif\r