--- /dev/null
+\r
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ vlvAccess.h\r
+\r
+Abstract:\r
+\r
+ Macros to simplify and abstract the interface to PCI configuration.\r
+\r
+--*/\r
+\r
+#ifndef _VLVACCESS_H_INCLUDED_\r
+#define _VLVACCESS_H_INCLUDED_\r
+\r
+#include "Valleyview.h"\r
+#include "VlvCommonDefinitions.h"\r
+#include <Library/IoLib.h>\r
+\r
+//\r
+// Memory Mapped IO access macros used by MSG BUS LIBRARY\r
+//\r
+#define MmioAddress( BaseAddr, Register ) \\r
+ ( (UINTN)BaseAddr + \\r
+ (UINTN)(Register) \\r
+ )\r
+\r
+\r
+//\r
+// UINT32\r
+//\r
+\r
+#define Mmio32Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio32( BaseAddr, Register ) \\r
+ *Mmio32Ptr( BaseAddr, Register )\r
+\r
+#define Mmio32Or( BaseAddr, Register, OrData ) \\r
+ Mmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ Mmio32( BaseAddr, Register ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+\r
+#define Mmio32And( BaseAddr, Register, AndData ) \\r
+ Mmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ Mmio32( BaseAddr, Register ) & \\r
+ (UINT32)(AndData) \\r
+ )\r
+\r
+#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ Mmio32( BaseAddr, Register ) = \\r
+ (UINT32) ( \\r
+ ( Mmio32( BaseAddr, Register ) & \\r
+ (UINT32)(AndData) \\r
+ ) | \\r
+ (UINT32)(OrData) \\r
+ )\r
+\r
+//\r
+// UINT16\r
+//\r
+\r
+#define Mmio16Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio16( BaseAddr, Register ) \\r
+ *Mmio16Ptr( BaseAddr, Register )\r
+\r
+#define Mmio16Or( BaseAddr, Register, OrData ) \\r
+ Mmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ Mmio16( BaseAddr, Register ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+\r
+#define Mmio16And( BaseAddr, Register, AndData ) \\r
+ Mmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ Mmio16( BaseAddr, Register ) & \\r
+ (UINT16)(AndData) \\r
+ )\r
+\r
+#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ Mmio16( BaseAddr, Register ) = \\r
+ (UINT16) ( \\r
+ ( Mmio16( BaseAddr, Register ) & \\r
+ (UINT16)(AndData) \\r
+ ) | \\r
+ (UINT16)(OrData) \\r
+ )\r
+\r
+//\r
+// UINT8\r
+//\r
+\r
+#define Mmio8Ptr( BaseAddr, Register ) \\r
+ ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio8( BaseAddr, Register ) \\r
+ *Mmio8Ptr( BaseAddr, Register )\r
+\r
+#define Mmio8Or( BaseAddr, Register, OrData ) \\r
+ Mmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ Mmio8( BaseAddr, Register ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+#define Mmio8And( BaseAddr, Register, AndData ) \\r
+ Mmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ Mmio8( BaseAddr, Register ) & \\r
+ (UINT8)(AndData) \\r
+ )\r
+\r
+#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+ Mmio8( BaseAddr, Register ) = \\r
+ (UINT8) ( \\r
+ ( Mmio8( BaseAddr, Register ) & \\r
+ (UINT8)(AndData) \\r
+ ) | \\r
+ (UINT8)(OrData) \\r
+ )\r
+\r
+//\r
+// MSG BUS API\r
+//\r
+\r
+#define MSG_BUS_ENABLED 0x000000F0\r
+#define MSGBUS_MASKHI 0xFFFFFF00\r
+#define MSGBUS_MASKLO 0x000000FF\r
+\r
+#define MESSAGE_BYTE_EN BIT4\r
+#define MESSAGE_WORD_EN BIT4 | BIT5\r
+#define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7\r
+\r
+#define SIDEBAND_OPCODE 0x78\r
+#define MEMREAD_OPCODE 0x00000000\r
+#define MEMWRITE_OPCODE 0x01000000\r
+\r
+\r
+\r
+/***************************/\r
+//\r
+// Memory mapped PCI IO\r
+//\r
+\r
+#define PciCfgPtr(Bus, Device, Function, Register )\\r
+ (UINTN)(Bus << 20) + \\r
+ (UINTN)(Device << 15) + \\r
+ (UINTN)(Function << 12) + \\r
+ (UINTN)(Register)\r
+\r
+#define PciCfg32Read_CF8CFC(B,D,F,R) \\r
+ (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))\r
+\r
+#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \\r
+ (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))\r
+\r
+#define PciCfg32Or_CF8CFC(B,D,F,R,O) \\r
+ PciCfg32Write_CF8CFC(B,D,F,R, \\r
+ (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))\r
+\r
+#define PciCfg32And_CF8CFC(B,D,F,R,A) \\r
+ PciCfg32Write_CF8CFC(B,D,F,R, \\r
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))\r
+\r
+#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \\r
+ PciCfg32Write_CF8CFC(B,D,F,R, \\r
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))\r
+\r
+//\r
+// Device 0, Function 0\r
+//\r
+#define McD0PciCfg64(Register) MmPci64 (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg32(Register) MmPci32 (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg16(Register) MmPci16 (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg8(Register) MmPci8 (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+\r
+//\r
+// Device 2, Function 0\r
+//\r
+#define McD2PciCfg64(Register) MmPci64 (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg64And(Register, AndData) MmPci64And (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg32(Register) MmPci32 (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg32And(Register, AndData) MmPci32And (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg16(Register) MmPci16 (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg16And(Register, AndData) MmPci16And (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg8(Register) MmPci8 (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg8And(Register, AndData) MmPci8And (0, MC_BUS, 2, 0, Register, AndData)\r
+\r
+//\r
+// IO\r
+//\r
+\r
+#ifndef IoIn8\r
+\r
+#define IoIn8(Port) \\r
+ IoRead8(Port)\r
+\r
+#define IoIn16(Port) \\r
+ IoRead16(Port)\r
+\r
+#define IoIn32(Port) \\r
+ IoRead32(Port)\r
+\r
+#define IoOut8(Port, Data) \\r
+ IoWrite8(Port, Data)\r
+\r
+#define IoOut16(Port, Data) \\r
+ IoWrite16(Port, Data)\r
+\r
+#define IoOut32(Port, Data) \\r
+ IoWrite32(Port, Data)\r
+\r
+#endif\r
+\r
+#endif\r
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