+++ /dev/null
-/*++\r
-\r
-Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
-\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-\r
-\r
-Module Name:\r
-\r
- PchRegsLpss.h\r
-\r
-Abstract:\r
-\r
- Register names for VLV Low Input Output (LPSS) module.\r
-\r
- Conventions:\r
-\r
- - Prefixes:\r
- Definitions beginning with "R_" are registers\r
- Definitions beginning with "B_" are bits within registers\r
- Definitions beginning with "V_" are meaningful values of bits within the registers\r
- Definitions beginning with "S_" are register sizes\r
- Definitions beginning with "N_" are the bit position\r
- - In general, PCH registers are denoted by "_PCH_" in register names\r
- - Registers / bits that are different between PCH generations are denoted by\r
- "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
- - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
- at the end of the register/bit names\r
- - Registers / bits of new devices introduced in a PCH generation will be just named\r
- as "_PCH_" without <generation_name> inserted.\r
-\r
---*/\r
-#ifndef _PCH_REGS_LPSS_H_\r
-#define _PCH_REGS_LPSS_H_\r
-\r
-\r
-//\r
-// Low Power Input Output (LPSS) Module Registers\r
-//\r
-\r
-//\r
-// LPSS DMAC Modules\r
-// PCI Config Space Registers\r
-//\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0 30\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1 24\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC 0\r
-\r
-#define R_PCH_LPSS_DMAC_DEVVENDID 0x00 // Device ID & Vendor ID\r
-#define B_PCH_LPSS_DMAC_DEVVENDID_DID 0xFFFF0000 // Device ID\r
-#define B_PCH_LPSS_DMAC_DEVVENDID_VID 0x0000FFFF // Vendor ID\r
-\r
-#define R_PCH_LPSS_DMAC_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_DMAC_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_DMAC_REVCC 0x08 // Revision ID & Class Code\r
-#define B_PCH_LPSS_DMAC_REVCC_CC 0xFFFFFF00 // Class Code\r
-#define B_PCH_LPSS_DMAC_REVCC_RID 0x000000FF // Revision ID\r
-\r
-#define R_PCH_LPSS_DMAC_CLHB 0x0C\r
-#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23\r
-#define B_PCH_LPSS_DMAC_CLHB_HT 0x007F0000 // Header Type\r
-#define B_PCH_LPSS_DMAC_CLHB_LT 0x0000FF00 // Latency Timer\r
-#define B_PCH_LPSS_DMAC_CLHB_CLS 0x000000FF // Cache Line Size\r
-\r
-#define R_PCH_LPSS_DMAC_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_DMAC_BAR_BA 0xFFFFC000 // Base Address\r
-#define V_PCH_LPSS_DMAC_BAR_SIZE 0x4000\r
-#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT 14\r
-#define B_PCH_LPSS_DMAC_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_DMAC_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_DMAC_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_DMAC_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_DMAC_SSID 0x2C // Sub System ID\r
-#define B_PCH_LPSS_DMAC_SSID_SID 0xFFFF0000 // Sub System ID\r
-#define B_PCH_LPSS_DMAC_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r
-\r
-#define R_PCH_LPSS_DMAC_ERBAR 0x30 // Expansion ROM BAR\r
-#define B_PCH_LPSS_DMAC_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r
-\r
-#define R_PCH_LPSS_DMAC_CAPPTR 0x34 // Capability Pointer\r
-#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r
-\r
-#define R_PCH_LPSS_DMAC_INTR 0x3C // Interrupt\r
-#define B_PCH_LPSS_DMAC_INTR_ML 0xFF000000 // Max Latency\r
-#define B_PCH_LPSS_DMAC_INTR_MG 0x00FF0000\r
-#define B_PCH_LPSS_DMAC_INTR_IP 0x00000F00 // Interrupt Pin\r
-#define B_PCH_LPSS_DMAC_INTR_IL 0x000000FF // Interrupt Line\r
-\r
-#define R_PCH_LPSS_DMAC_PCAPID 0x80 // Power Capability ID\r
-#define B_PCH_LPSS_DMAC_PCAPID_PS 0xF8000000 // PME Support\r
-#define B_PCH_LPSS_DMAC_PCAPID_VS 0x00070000 // Version\r
-#define B_PCH_LPSS_DMAC_PCAPID_NC 0x0000FF00 // Next Capability\r
-#define B_PCH_LPSS_DMAC_PCAPID_PC 0x000000FF // Power Capability\r
-\r
-#define R_PCH_LPSS_DMAC_PCS 0x84 // PME Control Status\r
-#define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status\r
-#define B_PCH_LPSS_DMAC_PCS_PMEEN BIT8 // PME Enable\r
-#define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset\r
-#define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State\r
-\r
-#define R_PCH_LPSS_DMAC_MANID 0xF8 // Manufacturer ID\r
-#define B_PCH_LPSS_DMAC_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r
-\r
-\r
-//\r
-// LPSS I2C Module\r
-// PCI Config Space Registers\r
-//\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C 24\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0 1\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1 2\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2 3\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3 4\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4 5\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5 6\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6 7\r
-\r
-#define R_PCH_LPSS_I2C_DEVVENDID 0x00 // Device ID & Vendor ID\r
-#define B_PCH_LPSS_I2C_DEVVENDID_DID 0xFFFF0000 // Device ID\r
-#define B_PCH_LPSS_I2C_DEVVENDID_VID 0x0000FFFF // Vendor ID\r
-\r
-#define R_PCH_LPSS_I2C_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_I2C_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_I2C_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_I2C_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_I2C_REVCC 0x08 // Revision ID & Class Code\r
-#define B_PCH_LPSS_I2C_REVCC_CC 0xFFFFFF00 // Class Code\r
-#define B_PCH_LPSS_I2C_REVCC_RID 0x000000FF // Revision ID\r
-\r
-#define R_PCH_LPSS_I2C_CLHB 0x0C\r
-#define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23\r
-#define B_PCH_LPSS_I2C_CLHB_HT 0x007F0000 // Header Type\r
-#define B_PCH_LPSS_I2C_CLHB_LT 0x0000FF00 // Latency Timer\r
-#define B_PCH_LPSS_I2C_CLHB_CLS 0x000000FF // Cache Line Size\r
-\r
-#define R_PCH_LPSS_I2C_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_I2C_BAR_BA 0xFFFFF000 // Base Address\r
-#define V_PCH_LPSS_I2C_BAR_SIZE 0x1000\r
-#define N_PCH_LPSS_I2C_BAR_ALIGNMENT 12\r
-#define B_PCH_LPSS_I2C_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_I2C_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_I2C_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_I2C_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_I2C_SSID 0x2C // Sub System ID\r
-#define B_PCH_LPSS_I2C_SSID_SID 0xFFFF0000 // Sub System ID\r
-#define B_PCH_LPSS_I2C_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r
-\r
-#define R_PCH_LPSS_I2C_ERBAR 0x30 // Expansion ROM BAR\r
-#define B_PCH_LPSS_I2C_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r
-\r
-#define R_PCH_LPSS_I2C_CAPPTR 0x34 // Capability Pointer\r
-#define B_PCH_LPSS_I2C_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r
-\r
-#define R_PCH_LPSS_I2C_INTR 0x3C // Interrupt\r
-#define B_PCH_LPSS_I2C_INTR_ML 0xFF000000 // Max Latency\r
-#define B_PCH_LPSS_I2C_INTR_MG 0x00FF0000\r
-#define B_PCH_LPSS_I2C_INTR_IP 0x00000F00 // Interrupt Pin\r
-#define B_PCH_LPSS_I2C_INTR_IL 0x000000FF // Interrupt Line\r
-\r
-#define R_PCH_LPSS_I2C_PCAPID 0x80 // Power Capability ID\r
-#define B_PCH_LPSS_I2C_PCAPID_PS 0xF8000000 // PME Support\r
-#define B_PCH_LPSS_I2C_PCAPID_VS 0x00070000 // Version\r
-#define B_PCH_LPSS_I2C_PCAPID_NC 0x0000FF00 // Next Capability\r
-#define B_PCH_LPSS_I2C_PCAPID_PC 0x000000FF // Power Capability\r
-\r
-#define R_PCH_LPSS_I2C_PCS 0x84 // PME Control Status\r
-#define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status\r
-#define B_PCH_LPSS_I2C_PCS_PMEEN BIT8 // PME Enable\r
-#define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset\r
-#define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State\r
-\r
-#define R_PCH_LPSS_I2C_MANID 0xF8 // Manufacturer ID\r
-#define B_PCH_LPSS_I2C_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r
-\r
-//\r
-// LPSS I2C Module\r
-// Memory Space Registers\r
-//\r
-#define R_PCH_LPSS_I2C_MEM_RESETS 0x804 // Software Reset\r
-#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-\r
-//\r
-// LPSS PWM Modules\r
-// PCI Config Space Registers\r
-//\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM 30\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0 1\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1 2\r
-\r
-#define R_PCH_LPSS_PWM_DEVVENDID 0x00 // Device ID & Vendor ID\r
-#define B_PCH_LPSS_PWM_DEVVENDID_DID 0xFFFF0000 // Device ID\r
-#define B_PCH_LPSS_PWM_DEVVENDID_VID 0x0000FFFF // Vendor ID\r
-\r
-#define R_PCH_LPSS_PWM_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_PWM_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_PWM_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_PWM_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_PWM_REVCC 0x08 // Revision ID & Class Code\r
-#define B_PCH_LPSS_PWM_REVCC_CC 0xFFFFFF00 // Class Code\r
-#define B_PCH_LPSS_PWM_REVCC_RID 0x000000FF // Revision ID\r
-\r
-#define R_PCH_LPSS_PWM_CLHB 0x0C\r
-#define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23\r
-#define B_PCH_LPSS_PWM_CLHB_HT 0x007F0000 // Header Type\r
-#define B_PCH_LPSS_PWM_CLHB_LT 0x0000FF00 // Latency Timer\r
-#define B_PCH_LPSS_PWM_CLHB_CLS 0x000000FF // Cache Line Size\r
-\r
-#define R_PCH_LPSS_PWM_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_PWM_BAR_BA 0xFFFFF000 // Base Address\r
-#define V_PCH_LPSS_PWM_BAR_SIZE 0x1000\r
-#define N_PCH_LPSS_PWM_BAR_ALIGNMENT 12\r
-#define B_PCH_LPSS_PWM_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_PWM_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_PWM_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_PWM_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_PWM_SSID 0x2C // Sub System ID\r
-#define B_PCH_LPSS_PWM_SSID_SID 0xFFFF0000 // Sub System ID\r
-#define B_PCH_LPSS_PWM_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r
-\r
-#define R_PCH_LPSS_PWM_ERBAR 0x30 // Expansion ROM BAR\r
-#define B_PCH_LPSS_PWM_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r
-\r
-#define R_PCH_LPSS_PWM_CAPPTR 0x34 // Capability Pointer\r
-#define B_PCH_LPSS_PWM_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r
-\r
-#define R_PCH_LPSS_PWM_INTR 0x3C // Interrupt\r
-#define B_PCH_LPSS_PWM_INTR_ML 0xFF000000 // Max Latency\r
-#define B_PCH_LPSS_PWM_INTR_MG 0x00FF0000\r
-#define B_PCH_LPSS_PWM_INTR_IP 0x00000F00 // Interrupt Pin\r
-#define B_PCH_LPSS_PWM_INTR_IL 0x000000FF // Interrupt Line\r
-\r
-#define R_PCH_LPSS_PWM_PCAPID 0x80 // Power Capability ID\r
-#define B_PCH_LPSS_PWM_PCAPID_PS 0xF8000000 // PME Support\r
-#define B_PCH_LPSS_PWM_PCAPID_VS 0x00070000 // Version\r
-#define B_PCH_LPSS_PWM_PCAPID_NC 0x0000FF00 // Next Capability\r
-#define B_PCH_LPSS_PWM_PCAPID_PC 0x000000FF // Power Capability\r
-\r
-#define R_PCH_LPSS_PWM_PCS 0x84 // PME Control Status\r
-#define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status\r
-#define B_PCH_LPSS_PWM_PCS_PMEEN BIT8 // PME Enable\r
-#define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset\r
-#define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State\r
-\r
-#define R_PCH_LPSS_PWM_MANID 0xF8 // Manufacturer ID\r
-#define B_PCH_LPSS_PWM_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r
-\r
-//\r
-// LPSS PWM Module\r
-// Memory Space Registers\r
-//\r
-#define R_PCH_LPSS_PWM_MEM_RESETS 0x804 // Software Reset\r
-#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-\r
-//\r
-// LPSS HSUART Modules\r
-// PCI Config Space Registers\r
-//\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART 30\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0 3\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1 4\r
-\r
-#define R_PCH_LPSS_HSUART_DEVVENDID 0x00 // Device ID & Vendor ID\r
-#define B_PCH_LPSS_HSUART_DEVVENDID_DID 0xFFFF0000 // Device ID\r
-#define B_PCH_LPSS_HSUART_DEVVENDID_VID 0x0000FFFF // Vendor ID\r
-\r
-#define R_PCH_LPSS_HSUART_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_HSUART_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_HSUART_REVCC 0x08 // Revision ID & Class Code\r
-#define B_PCH_LPSS_HSUART_REVCC_CC 0xFFFFFF00 // Class Code\r
-#define B_PCH_LPSS_HSUART_REVCC_RID 0x000000FF // Revision ID\r
-\r
-#define R_PCH_LPSS_HSUART_CLHB 0x0C\r
-#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23\r
-#define B_PCH_LPSS_HSUART_CLHB_HT 0x007F0000 // Header Type\r
-#define B_PCH_LPSS_HSUART_CLHB_LT 0x0000FF00 // Latency Timer\r
-#define B_PCH_LPSS_HSUART_CLHB_CLS 0x000000FF // Cache Line Size\r
-\r
-#define R_PCH_LPSS_HSUART_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_HSUART_BAR_BA 0xFFFFF000 // Base Address\r
-#define V_PCH_LPSS_HSUART_BAR_SIZE 0x1000\r
-#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT 12\r
-#define B_PCH_LPSS_HSUART_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_HSUART_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_HSUART_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_HSUART_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_HSUART_SSID 0x2C // Sub System ID\r
-#define B_PCH_LPSS_HSUART_SSID_SID 0xFFFF0000 // Sub System ID\r
-#define B_PCH_LPSS_HSUART_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r
-\r
-#define R_PCH_LPSS_HSUART_ERBAR 0x30 // Expansion ROM BAR\r
-#define B_PCH_LPSS_HSUART_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r
-\r
-#define R_PCH_LPSS_HSUART_CAPPTR 0x34 // Capability Pointer\r
-#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r
-\r
-#define R_PCH_LPSS_HSUART_INTR 0x3C // Interrupt\r
-#define B_PCH_LPSS_HSUART_INTR_ML 0xFF000000 // Max Latency\r
-#define B_PCH_LPSS_HSUART_INTR_MG 0x00FF0000\r
-#define B_PCH_LPSS_HSUART_INTR_IP 0x00000F00 // Interrupt Pin\r
-#define B_PCH_LPSS_HSUART_INTR_IL 0x000000FF // Interrupt Line\r
-\r
-#define R_PCH_LPSS_HSUART_PCAPID 0x80 // Power Capability ID\r
-#define B_PCH_LPSS_HSUART_PCAPID_PS 0xF8000000 // PME Support\r
-#define B_PCH_LPSS_HSUART_PCAPID_VS 0x00070000 // Version\r
-#define B_PCH_LPSS_HSUART_PCAPID_NC 0x0000FF00 // Next Capability\r
-#define B_PCH_LPSS_HSUART_PCAPID_PC 0x000000FF // Power Capability\r
-\r
-#define R_PCH_LPSS_HSUART_PCS 0x84 // PME Control Status\r
-#define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status\r
-#define B_PCH_LPSS_HSUART_PCS_PMEEN BIT8 // PME Enable\r
-#define B_PCH_LPSS_HSUART_PCS_NSS BIT3 // No Soft Reset\r
-#define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State\r
-\r
-#define R_PCH_LPSS_HSUART_MANID 0xF8 // Manufacturer ID\r
-#define B_PCH_LPSS_HSUART_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r
-\r
-//\r
-// LPSS HSUART Module\r
-// Memory Space Registers\r
-//\r
-#define R_PCH_LPSS_HSUART_MEM_PCP 0x800 // Private Clock Parameters\r
-#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update\r
-#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider\r
-#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider\r
-#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable\r
-\r
-#define R_PCH_LPSS_HSUART_MEM_RESETS 0x804 // Software Reset\r
-#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-\r
-//\r
-// LPSS SPI Module\r
-// PCI Config Space Registers\r
-//\r
-#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI 30\r
-#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI 5\r
-\r
-#define R_PCH_LPSS_SPI_DEVVENDID 0x00 // Device ID & Vendor ID\r
-#define B_PCH_LPSS_SPI_DEVVENDID_DID 0xFFFF0000 // Device ID\r
-#define B_PCH_LPSS_SPI_DEVVENDID_VID 0x0000FFFF // Vendor ID\r
-\r
-#define R_PCH_LPSS_SPI_STSCMD 0x04 // Status & Command\r
-#define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA\r
-#define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA\r
-#define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List\r
-#define B_PCH_LPSS_SPI_STSCMD_INTRSTS BIT19 // Interrupt Status\r
-#define B_PCH_LPSS_SPI_STSCMD_INTRDIS BIT10 // Interrupt Disable\r
-#define B_PCH_LPSS_SPI_STSCMD_SERREN BIT8 // SERR# Enable\r
-#define B_PCH_LPSS_SPI_STSCMD_BME BIT2 // Bus Master Enable\r
-#define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable\r
-\r
-#define R_PCH_LPSS_SPI_REVCC 0x08 // Revision ID & Class Code\r
-#define B_PCH_LPSS_SPI_REVCC_CC 0xFFFFFF00 // Class Code\r
-#define B_PCH_LPSS_SPI_REVCC_RID 0x000000FF // Revision ID\r
-\r
-#define R_PCH_LPSS_SPI_CLHB 0x0C\r
-#define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23\r
-#define B_PCH_LPSS_SPI_CLHB_HT 0x007F0000 // Header Type\r
-#define B_PCH_LPSS_SPI_CLHB_LT 0x0000FF00 // Latency Timer\r
-#define B_PCH_LPSS_SPI_CLHB_CLS 0x000000FF // Cache Line Size\r
-\r
-#define R_PCH_LPSS_SPI_BAR 0x10 // BAR\r
-#define B_PCH_LPSS_SPI_BAR_BA 0xFFFFF000 // Base Address\r
-#define V_PCH_LPSS_SPI_BAR_SIZE 0x1000\r
-#define N_PCH_LPSS_SPI_BAR_ALIGNMENT 12\r
-#define B_PCH_LPSS_SPI_BAR_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_SPI_BAR_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_SPI_BAR1 0x14 // BAR 1\r
-#define B_PCH_LPSS_SPI_BAR1_BA 0xFFFFF000 // Base Address\r
-#define B_PCH_LPSS_SPI_BAR1_SI 0x00000FF0 // Size Indicator\r
-#define B_PCH_LPSS_SPI_BAR1_PF BIT3 // Prefetchable\r
-#define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type\r
-#define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space\r
-\r
-#define R_PCH_LPSS_SPI_SSID 0x2C // Sub System ID\r
-#define B_PCH_LPSS_SPI_SSID_SID 0xFFFF0000 // Sub System ID\r
-#define B_PCH_LPSS_SPI_SSID_SVID 0x0000FFFF // Sub System Vendor ID\r
-\r
-#define R_PCH_LPSS_SPI_ERBAR 0x30 // Expansion ROM BAR\r
-#define B_PCH_LPSS_SPI_ERBAR_BA 0xFFFFFFFF // Expansion ROM Base Address\r
-\r
-#define R_PCH_LPSS_SPI_CAPPTR 0x34 // Capability Pointer\r
-#define B_PCH_LPSS_SPI_CAPPTR_CPPWR 0xFF // Capability Pointer Power\r
-\r
-#define R_PCH_LPSS_SPI_INTR 0x3C // Interrupt\r
-#define B_PCH_LPSS_SPI_INTR_ML 0xFF000000 // Max Latency\r
-#define B_PCH_LPSS_SPI_INTR_MG 0x00FF0000\r
-#define B_PCH_LPSS_SPI_INTR_IP 0x00000F00 // Interrupt Pin\r
-#define B_PCH_LPSS_SPI_INTR_IL 0x000000FF // Interrupt Line\r
-\r
-#define R_PCH_LPSS_SPI_PCAPID 0x80 // Power Capability ID\r
-#define B_PCH_LPSS_SPI_PCAPID_PS 0xF8000000 // PME Support\r
-#define B_PCH_LPSS_SPI_PCAPID_VS 0x00070000 // Version\r
-#define B_PCH_LPSS_SPI_PCAPID_NC 0x0000FF00 // Next Capability\r
-#define B_PCH_LPSS_SPI_PCAPID_PC 0x000000FF // Power Capability\r
-\r
-#define R_PCH_LPSS_SPI_PCS 0x84 // PME Control Status\r
-#define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status\r
-#define B_PCH_LPSS_SPI_PCS_PMEEN BIT8 // PME Enable\r
-#define B_PCH_LPSS_SPI_PCS_NSS BIT3 // No Soft Reset\r
-#define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State\r
-\r
-#define R_PCH_LPSS_SPI_MANID 0xF8 // Manufacturer ID\r
-#define B_PCH_LPSS_SPI_MANID_MANID 0xFFFFFFFF // Manufacturer ID\r
-\r
-//\r
-// LPSS SPI Module\r
-// Memory Space Registers\r
-//\r
-#define R_PCH_LPSS_SPI_MEM_PCP 0x400 // Private Clock Parameters\r
-#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE BIT31 // Clock Divider Update\r
-#define B_PCH_LPSS_SPI_MEM_PCP_NVAL 0x7FFF0000 // N value for the M over N divider\r
-#define B_PCH_LPSS_SPI_MEM_PCP_MVAL 0x0000FFFE // M value for the M over N divider\r
-#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable\r
-\r
-#define R_PCH_LPSS_SPI_MEM_RESETS 0x404 // Software Reset\r
-#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset\r
-#define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset\r
-\r
-#endif\r
projects / mirror_edk2.git / blobdiff