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[mirror_edk2.git] / Vlv2DeviceRefCodePkg / ValleyView2Soc / SouthCluster / Include / PchRegs / PchRegsUsb.h

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h
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+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsUsb.h\r
+\r
+  @brief\r
+  Register names for PCH USB devices.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_USB_H_\r
+#define _PCH_REGS_USB_H_\r
+\r
+///\r
+/// USB Definitions\r
+///\r
+\r
+typedef enum {\r
+  PchEhci1 = 0,\r
+  PchEhciControllerMax\r
+} PCH_USB20_CONTROLLER_TYPE;\r
+\r
+#define PCH_USB_MAX_PHYSICAL_PORTS          4      /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.\r
+#define PCH_EHCI_MAX_PORTS                  4      /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.\r
+#define PCH_HSIC_MAX_PORTS                  2\r
+#define PCH_XHCI_MAX_USB3_PORTS             1\r
+\r
+#define PCI_DEVICE_NUMBER_PCH_USB           29\r
+#define PCI_FUNCTION_NUMBER_PCH_EHCI        0\r
+\r
+#define R_PCH_USB_VENDOR_ID                 0x00  // Vendor ID\r
+#define V_PCH_USB_VENDOR_ID                 V_PCH_INTEL_VENDOR_ID\r
+\r
+#define R_PCH_USB_DEVICE_ID                 0x02  // Device ID\r
+#define V_PCH_USB_DEVICE_ID_0               0x0F34  // EHCI#1\r
+\r
+#define R_PCH_EHCI_SVID                     0x2C  // USB2 Subsystem Vendor ID\r
+#define B_PCH_EHCI_SVID                     0xFFFF // USB2 Subsystem Vendor ID Mask\r
+\r
+#define R_PCH_EHCI_PWR_CNTL_STS             0x54  // Power Management Control / Status\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS     BIT15 // PME Status\r
+#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13) // Data Scale\r
+#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9) // Data Select\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN      BIT8  // Power Enable\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0) // Power State\r
+#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0  0     // D0 State\r
+#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0) // D3 Hot State\r
+\r
+///\r
+/// USB3 (XHCI) related definitions\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_XHCI          20\r
+#define PCI_FUNCTION_NUMBER_PCH_XHCI        0\r
+//\r
+/////\r
+///// XHCI PCI Config Space registers\r
+/////\r
+\r
+#define R_PCH_XHCI_SVID                     0x2C\r
+#define B_PCH_XHCI_SVID                     0xFFFF\r
+\r
+\r
+#define R_PCH_XHCI_PWR_CNTL_STS             0x74\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS     BIT15\r
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13)\r
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9)\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN      BIT8\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0)\r
+#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0)\r
+\r
+#endif\r