+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ Gpio.h\r
+\r
+Abstract:\r
+\r
+EFI 2.0 PEIM to provide platform specific information to other\r
+modules and to do some platform specific initialization.\r
+\r
+--*/\r
+\r
+#ifndef _PEI_GPIO_H\r
+#define _PEI_GPIO_H\r
+\r
+//#include "Efi.h"\r
+//#include "EfiCommonLib.h"\r
+//#include "Pei.h"\r
+//#include "Numbers.h"\r
+\r
+////\r
+//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)\r
+////\r
+//// Field Descriptions:\r
+//// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.\r
+//// I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
+//// (Note: Only meaningful for pins used as GPIOs.)\r
+//// LVL: This field gives you the initial value for "output" GPIO's.\r
+//// (Note: The output level is dependent upon whether the pin is inverted.)\r
+//// INV: Defines whether Input GPIOs activation level is inverted.\r
+//// (Note: Only affects the level sent to the GPE logic and does not\r
+//// affect the level read through the GPIO registers.)\r
+////\r
+//// Notes:\r
+//// 1. BoardID is GPIO [8:38:34]\r
+////\r
+////Signal UsedAs USE I/O LVL INV\r
+////--------------------------------------------------------------------------\r
+////GPIO0 Nonfunction G O H -\r
+////GPIO1 SMC_RUNTIME_SCI# G I - I\r
+////PIRQE#/GPIO2 Nonfunction G O H -\r
+////PIRQF#/GPIO3 Nonfunction G O H -\r
+////PIRQG#/GPIO4 Nonfunction G O H -\r
+////PIRQH#/GPIO5 Nonfunction G O H -\r
+////GPIO6 unused G O L -\r
+////GPIO7 unused G O L -\r
+////GPIO8 BOARD ID2 G I - -\r
+////GPIO9 unused G O L -\r
+////GPIO10 SMC_EXTSMI# G I - I\r
+////GPIO11 Nonfunction G O H -\r
+////GPIO12 unused G O L -\r
+////GPIO13 SMC_WAKE_SCI# G I - I\r
+////GPIO14 unused G O L -\r
+////GPIO15 unused G O L -\r
+////GPIO16 PM_DPRSLPVR N - - -\r
+////GNT5#/GPIO17 GNT5# N - - -\r
+////STPPCI#/GPIO18 PM_STPPCI# N - - -\r
+////STPCPU#/GPIO20 PM_STPCPU# N - - -\r
+////GPIO22 CRT_RefClk G I - -\r
+////GPIO23 unused G O L -\r
+////GPIO24 unused G O L -\r
+////GPIO25 DMI strap G O L -\r
+////GPIO26 unused G O L -\r
+////GPIO27 unused G O L -\r
+////GPIO28 RF_KILL# G O H -\r
+////OC5#/GPIO29 OC N - - -\r
+////OC6#/GPIO30 OC N - - -\r
+////OC7#/GPIO31 OC N - - -\r
+////CLKRUN#/GPIO32 PM_CLKRUN# N - - -\r
+////GPIO33 NC G O L -\r
+////GPIO34 BOARD ID0 G I - -\r
+////GPIO36 unused G O L -\r
+////GPIO38 BOARD ID1 G I - -\r
+////GPIO39 unused G O L -\r
+////GPIO48 unused G O L -\r
+////CPUPWRGD/GPIO49 H_PWRGD N - - -\r
+//\r
+//#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal\r
+//#define GPIO_USE_SEL2_VAL 0x000100D6\r
+//#define GPIO_IO_SEL_VAL 0x00402502\r
+//#define GPIO_IO_SEL2_VAL 0x00000044\r
+//#define GPIO_LVL_VAL 0x1800083D\r
+//#define GPIO_LVL2_VAL 0x00000000\r
+//#define GPIO_INV_VAL 0x00002402\r
+//#define GPIO_BLNK_VAL 0x00000000\r
+//#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
+\r
+//\r
+// GPIO Register Settings for CedarRock and CedarFalls platforms\r
+//\r
+// GPIO Register Settings for NB10_CRB\r
+//---------------------------------------------------------------------------------\r
+//Signal Used As USE I/O LVL\r
+//---------------------------------------------------------------------------------\r
+//\r
+// GPIO0 FP_AUDIO_DETECT G I\r
+// GPIO1 SMC_RUNTIME_SCI# G I\r
+// GPIO2 INT_PIRQE_N N I\r
+// GPIO3 INT_PIRQF_N N I\r
+// GPIO4 INT_PIRQG_N N I\r
+// GPIO5 INT_PIRQH_N N I\r
+// GPIO6\r
+// GPIO7\r
+// GPIO8\r
+// GPIO9 LPC_SIO_PME G I\r
+// GPIO10 SMC_EXTSMI_N G I\r
+// GPIO11 SMBALERT- pullup N\r
+// GPIO12 ICH_GP12 G I\r
+// GPIO13 SMC_WAKE_SCI_N G I\r
+// GPIO14 LCD_PID0 G O H\r
+// GPIO15 CONFIG_MODE_N G I\r
+// GPIO16 PM_DPRSLPVR N\r
+// GPIO17 SPI_SELECT_STRAP1\r
+// /L_BKLTSEL0_N G I\r
+// GPIO18 PM_STPPCI_N N\r
+// GPIO19\r
+// GPIO20 PM_STPCPU_N N\r
+// GPIO21\r
+// GPIO22 REQ4B G I\r
+// GPIO23 L_DRQ1_N N\r
+// GPIO24 CRB_SV_DET_N G O H\r
+// GPIO25 DMI strap\r
+// / L_BKLTSEL1_N G O H\r
+// GPIO26 LCD_PID1 G O H\r
+// GPIO27 TPEV_DDR3L_DETECT G O H\r
+// GPIO28 RF_KILL G O H:enable\r
+// GPIO29 OC N\r
+// GPIO30 OC N\r
+// GPIO31 OC N\r
+// GPIO32 PM_CLKRUN_N Native\r
+// GPIO33 MFG_MODE_N G I\r
+// GPIO34 BOARD ID0 G I\r
+// GPIO35\r
+// GPIO36 SV_SET_UP G O H\r
+// GPIO37\r
+// GPIO38 BOARD ID1 G I\r
+// GPIO39 BOARD ID2 G I\r
+// GPIO48 FLASH_SEL0 N\r
+// GPIO49 H_PWRGD N\r
+\r
+#define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))\r
+#define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))\r
+\r
+#define GPIO_USE_SEL_VAL 0X1F42F7C3\r
+#define GPIO_USE_SEL2_VAL 0X000000D6\r
+#define GPIO_IO_SEL_VAL 0X1042B73F\r
+#define GPIO_IO_SEL2_VAL 0X000100C6\r
+#define GPIO_LVL_VAL 0X1F15F601\r
+#define GPIO_LVL2_VAL 0X000200D7\r
+#define GPIO_INV_VAL 0x00002602\r
+#define GPIO_BLNK_VAL 0x00040000\r
+#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
+\r
+#endif\r
projects / mirror_edk2.git / blobdiff