--- /dev/null
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+ @file\r
+ PchPlatformPolicy.h\r
+\r
+ @brief\r
+ PCH policy protocol produced by a platform driver specifying various\r
+ expected PCH settings. This protocol is consumed by the PCH drivers.\r
+\r
+**/\r
+#ifndef _PCH_PLATFORM_POLICY_H_\r
+#define _PCH_PLATFORM_POLICY_H_\r
+\r
+\r
+//\r
+#include "PchRegs.h"\r
+#ifndef ECP_FLAG\r
+#include "Uefi.h"\r
+#endif\r
+\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \\r
+ { \\r
+ 0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \\r
+ }\r
+extern EFI_GUID gDxePchPlatformPolicyProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL DXE_PCH_PLATFORM_POLICY_PROTOCOL;\r
+\r
+///\r
+/// Protocol revision number\r
+/// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+/// Major changes will require publication of a new protocol\r
+///\r
+/// Revision 1: Original version\r
+///\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12\r
+\r
+///\r
+/// Generic definitions for device enabling/disabling used by PCH code.\r
+///\r
+#define PCH_DEVICE_ENABLE 1\r
+#define PCH_DEVICE_DISABLE 0\r
+\r
+///\r
+/// ---------------------------- Device Enabling ------------------------------\r
+///\r
+/// PCH Device enablings\r
+///\r
+typedef struct {\r
+ UINT8 Lan : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto\r
+ UINT8 Sata : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Smbus : 1; /// 0: Disable; 1: Enable\r
+ UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
+ UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change\r
+} PCH_DEVICE_ENABLING;\r
+\r
+///\r
+/// ---------------------------- USB Config -----------------------------\r
+///\r
+///\r
+/// Overcurrent pins\r
+///\r
+typedef enum {\r
+ PchUsbOverCurrentPin0 = 0,\r
+ PchUsbOverCurrentPin1,\r
+ PchUsbOverCurrentPin2,\r
+ PchUsbOverCurrentPin3,\r
+ PchUsbOverCurrentPin4,\r
+ PchUsbOverCurrentPin5,\r
+ PchUsbOverCurrentPin6,\r
+ PchUsbOverCurrentPin7,\r
+ PchUsbOverCurrentPinSkip,\r
+ PchUsbOverCurrentPinMax\r
+} PCH_USB_OVERCURRENT_PIN;\r
+\r
+typedef struct {\r
+ UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled\r
+ UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port.\r
+ UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port.\r
+ UINT8 Rsvdbits : 5;\r
+} PCH_USB_PORT_SETTINGS;\r
+\r
+typedef struct {\r
+ UINT8 Enable : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Rsvdbits : 7;\r
+} PCH_USB20_CONTROLLER_SETTINGS;\r
+\r
+typedef struct {\r
+ UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
+ UINT8 Rsvdbits : 6;\r
+} PCH_USBOTG_CONTROLLER_SETTINGS;\r
+\r
+#define PCH_XHCI_MODE_OFF 0\r
+#define PCH_XHCI_MODE_ON 1\r
+#define PCH_XHCI_MODE_AUTO 2\r
+#define PCH_XHCI_MODE_SMARTAUTO 3\r
+\r
+#define PCH_EHCI_DEBUG_OFF 0\r
+#define PCH_EHCI_DEBUG_ON 1\r
+\r
+#define PCH_USB_FRONT_PANEL 1\r
+#define PCH_USB_BACK_PANEL 0\r
+\r
+typedef struct {\r
+ UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto\r
+ UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available\r
+ UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Rsvdbits : 4;\r
+} PCH_USB30_CONTROLLER_SETTINGS;\r
+\r
+typedef struct {\r
+ UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control\r
+ UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR\r
+ UINT8 RsvdBits : 6;\r
+ PCH_USB_PORT_SETTINGS PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];\r
+ PCH_USB20_CONTROLLER_SETTINGS Usb20Settings[PchEhciControllerMax];\r
+ PCH_USB30_CONTROLLER_SETTINGS Usb30Settings;\r
+ PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;\r
+ PCH_USB_OVERCURRENT_PIN Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];\r
+ PCH_USB_OVERCURRENT_PIN Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];\r
+ ///\r
+ /// The length of Usb Port to configure the USB transmitter,\r
+ /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point.\r
+ ///\r
+ UINT16 Usb20PortLength[PCH_EHCI_MAX_PORTS];\r
+ UINT16 EhciDebug;\r
+ UINT16 UsbXhciLpmSupport;\r
+\r
+} PCH_USB_CONFIG;\r
+\r
+///\r
+/// ---------------------------- PCI Express Config ----------------------\r
+///\r
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature\r
+///\r
+typedef enum {\r
+ PchPcieAspmDisabled,\r
+ PchPcieAspmL0s,\r
+ PchPcieAspmL1,\r
+ PchPcieAspmL0sL1,\r
+ PchPcieAspmAutoConfig,\r
+ PchPcieAspmMax\r
+} PCH_PCI_EXPRESS_ASPM_CONTROL;\r
+\r
+///\r
+/// Refer to PCH EDS for the PCH implementation values corresponding\r
+/// to below PCI-E spec defined ranges\r
+///\r
+typedef enum {\r
+ PchPciECompletionTO_Default,\r
+ PchPciECompletionTO_50_100us,\r
+ PchPciECompletionTO_1_10ms,\r
+ PchPciECompletionTO_16_55ms,\r
+ PchPciECompletionTO_65_210ms,\r
+ PchPciECompletionTO_260_900ms,\r
+ PchPciECompletionTO_1_3P5s,\r
+ PchPciECompletionTO_4_13s,\r
+ PchPciECompletionTO_17_64s,\r
+ PchPciECompletionTO_Disabled\r
+} PCH_PCIE_COMPLETION_TIMEOUT;\r
+\r
+typedef struct {\r
+ UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable.\r
+ UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port\r
+ UINT8 SlotImplemented : 1;\r
+ UINT8 HotPlug : 1;\r
+ UINT8 PmSci : 1;\r
+ UINT8 ExtSync : 1; /// Extended Synch\r
+ UINT8 Rsvdbits : 2;\r
+ ///\r
+ /// Error handlings\r
+ ///\r
+ UINT8 UnsupportedRequestReport : 1;\r
+ UINT8 FatalErrorReport : 1;\r
+ UINT8 NoFatalErrorReport : 1;\r
+ UINT8 CorrectableErrorReport : 1;\r
+ UINT8 PmeInterrupt : 1;\r
+ UINT8 SystemErrorOnFatalError : 1;\r
+ UINT8 SystemErrorOnNonFatalError : 1;\r
+ UINT8 SystemErrorOnCorrectableError : 1;\r
+\r
+ UINT8 AdvancedErrorReporting : 1;\r
+ UINT8 TransmitterHalfSwing : 1;\r
+ UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change\r
+\r
+ UINT8 FunctionNumber; /// The function number this root port is mapped to.\r
+ UINT8 PhysicalSlotNumber;\r
+ PCH_PCIE_COMPLETION_TIMEOUT CompletionTimeout;\r
+ PCH_PCI_EXPRESS_ASPM_CONTROL Aspm;\r
+} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;\r
+\r
+typedef struct {\r
+ /**\r
+ VendorId\r
+\r
+ The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID\r
+\r
+ DeviceId\r
+\r
+ The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID\r
+\r
+ RevId\r
+\r
+ The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings\r
+\r
+ BaseClassCode\r
+\r
+ The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class\r
+\r
+ SubClassCode\r
+\r
+ The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class\r
+\r
+\r
+ EndPointAspm\r
+\r
+ The override ASPM setting from End point\r
+ **/\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT8 RevId;\r
+ UINT8 BaseClassCode;\r
+ UINT8 SubClassCode;\r
+ PCH_PCI_EXPRESS_ASPM_CONTROL EndPointAspm;\r
+} PCH_PCIE_DEVICE_ASPM_OVERRIDE;\r
+\r
+typedef struct {\r
+ UINT16 VendorId; ///< PCI configuration space offset 0\r
+ UINT16 DeviceId; ///< PCI configuration space offset 2\r
+ UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings\r
+ /**\r
+ SnoopLatency bit definition\r
+ Note: All Reserved bits must be set to 0\r
+\r
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid\r
+ When clear values in bits 9:0 will be ignored\r
+ BITS[14:13] - Reserved\r
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
+ 000b - 1 ns\r
+ 001b - 32 ns\r
+ 010b - 1024 ns\r
+ 011b - 32,768 ns\r
+ 100b - 1,048,576 ns\r
+ 101b - 33,554,432 ns\r
+ 110b - Reserved\r
+ 111b - Reserved\r
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with\r
+ the scale in bits 12:10\r
+ **/\r
+ UINT16 SnoopLatency;\r
+ /**\r
+ NonSnoopLatency bit definition\r
+ Note: All Reserved bits must be set to 0\r
+\r
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid\r
+ When clear values in bits 9:0 will be ignored\r
+ BITS[14:13] - Reserved\r
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
+ 000b - 1 ns\r
+ 001b - 32 ns\r
+ 010b - 1024 ns\r
+ 011b - 32,768 ns\r
+ 100b - 1,048,576 ns\r
+ 101b - 33,554,432 ns\r
+ 110b - Reserved\r
+ 111b - Reserved\r
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with\r
+ the scale in bits 12:10\r
+ **/\r
+ UINT16 NonSnoopLatency;\r
+} PCH_PCIE_DEVICE_LTR_OVERRIDE;\r
+\r
+typedef struct {\r
+ ///\r
+ /// Temp Bus Number range available to be assigned to\r
+ /// each root port and its downstream devices for initialization\r
+ /// of these devices before PCI Bus enumeration\r
+ ///\r
+ UINT8 TempRootPortBusNumMin;\r
+ UINT8 TempRootPortBusNumMax;\r
+ PCH_PCI_EXPRESS_ROOT_PORT_CONFIG RootPort[PCH_PCIE_MAX_ROOT_PORTS];\r
+ BOOLEAN RootPortClockGating;\r
+ UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override\r
+ PCH_PCIE_DEVICE_ASPM_OVERRIDE *DevAspmOverride; /// The Pointer which is point to Pci Express card Aspm setting override\r
+ UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318.\r
+} PCH_PCI_EXPRESS_CONFIG;\r
+\r
+\r
+///\r
+/// ---------------------------- SATA Config -----------------------------\r
+///\r
+typedef enum {\r
+ PchSataSpeedSupportGen1 = 1,\r
+ PchSataSpeedSupportGen2\r
+} PCH_SATA_SPEED_SUPPORT;\r
+\r
+typedef struct {\r
+ UINT8 Enable : 1; /// 0: Disable; 1: Enable\r
+ UINT8 HotPlug : 1; /// 0: Disable; 1: Enable\r
+ UINT8 MechSw : 1; /// 0: Disable; 1: Enable\r
+ UINT8 External : 1; /// 0: Disable; 1: Enable\r
+ UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device\r
+ UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change\r
+} PCH_SATA_PORT_SETTINGS;\r
+\r
+typedef struct {\r
+ PCH_SATA_PORT_SETTINGS PortSettings[PCH_AHCI_MAX_PORTS];\r
+ UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0\r
+ UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1\r
+ UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10\r
+ UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5\r
+ UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology\r
+ UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER\r
+ UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled\r
+\r
+ UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS\r
+ UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports\r
+ UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes\r
+ UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management\r
+ UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode\r
+ UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support\r
+ /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)\r
+\r
+ UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change\r
+} PCH_SATA_CONFIG;\r
+///\r
+/// --------------------------- AZALIA Config ------------------------------\r
+///\r
+typedef struct {\r
+ UINT32 VendorDeviceId;\r
+ UINT16 SubSystemId;\r
+ UINT8 RevisionId; /// 0xFF applies to all steppings\r
+ UINT8 FrontPanelSupport;\r
+ UINT16 NumberOfRearJacks;\r
+ UINT16 NumberOfFrontJacks;\r
+} PCH_AZALIA_VERB_TABLE_HEADER;\r
+\r
+typedef struct {\r
+ PCH_AZALIA_VERB_TABLE_HEADER VerbTableHeader;\r
+ UINT32 *VerbTableData;\r
+} PCH_AZALIA_VERB_TABLE;\r
+\r
+typedef struct {\r
+ UINT8 Pme : 1; /// 0: Disable; 1: Enable\r
+ UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported\r
+ UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached\r
+ UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable\r
+ UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable\r
+ UINT8 Rsvdbits : 3;\r
+ UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform\r
+ PCH_AZALIA_VERB_TABLE *AzaliaVerbTable; /// Pointer to the actual verb table(s)\r
+ UINT16 ResetWaitTimer; /// The delay timer after Azalia reset, the value is number of microseconds\r
+} PCH_AZALIA_CONFIG;\r
+\r
+///\r
+/// --------------------------- Smbus Config ------------------------------\r
+///\r
+typedef struct {\r
+ UINT8 NumRsvdSmbusAddresses;\r
+ UINT8 *RsvdSmbusAddressTable;\r
+} PCH_SMBUS_CONFIG;\r
+\r
+///\r
+/// --------------------------- Miscellaneous PM Config ------------------------------\r
+///\r
+typedef struct {\r
+ UINT8 MeWakeSts : 1;\r
+ UINT8 MeHrstColdSts : 1;\r
+ UINT8 MeHrstWarmSts : 1;\r
+ UINT8 MeHostPowerDn : 1;\r
+ UINT8 WolOvrWkSts : 1;\r
+ UINT8 Rsvdbits : 3;\r
+} PCH_POWER_RESET_STATUS;\r
+\r
+typedef struct {\r
+ UINT8 PmeB0S5Dis : 1;\r
+ UINT8 WolEnableOverride : 1;\r
+ UINT8 Rsvdbits : 6;\r
+} PCH_WAKE_CONFIG;\r
+\r
+typedef enum {\r
+ PchSlpS360us,\r
+ PchSlpS31ms,\r
+ PchSlpS350ms,\r
+ PchSlpS32s\r
+} PCH_SLP_S3_MIN_ASSERT;\r
+\r
+typedef enum {\r
+ PchSlpS4PchTime, /// The time defined in EDS Power Sequencing and Reset Signal Timings table\r
+ PchSlpS41s,\r
+ PchSlpS42s,\r
+ PchSlpS43s,\r
+ PchSlpS44s\r
+} PCH_SLP_S4_MIN_ASSERT;\r
+\r
+typedef struct {\r
+ ///\r
+ /// Specify which Power/Reset bits need to be cleared by\r
+ /// the PCH Init Driver.\r
+ /// Usually platform drivers take care of these bits, but if\r
+ /// not, let PCH Init driver clear the bits.\r
+ ///\r
+ PCH_POWER_RESET_STATUS PowerResetStatusClear;\r
+ ///\r
+ /// Specify Wake Policy\r
+ ///\r
+ PCH_WAKE_CONFIG WakeConfig;\r
+ ///\r
+ /// SLP_XX Minimum Assertion Width Policy\r
+ ///\r
+ PCH_SLP_S3_MIN_ASSERT PchSlpS3MinAssert;\r
+ PCH_SLP_S4_MIN_ASSERT PchSlpS4MinAssert;\r
+ UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up\r
+ UINT8 SlpLanLowDc : 1;\r
+ UINT8 Rsvdbits : 6;\r
+} PCH_MISC_PM_CONFIG;\r
+\r
+///\r
+/// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----\r
+///\r
+typedef struct {\r
+ UINT16 SubSystemVendorId;\r
+ UINT16 SubSystemId;\r
+} PCH_DEFAULT_SVID_SID;\r
+\r
+///\r
+/// --------------------------- Lock Down Config ------------------------------\r
+///\r
+typedef struct {\r
+ UINT8 GlobalSmi : 1;\r
+ UINT8 BiosInterface : 1;\r
+ UINT8 RtcLock : 1;\r
+ UINT8 BiosLock : 1;\r
+ UINT8 Rsvdbits : 4;\r
+ UINT8 PchBiosLockSwSmiNumber;\r
+} PCH_LOCK_DOWN_CONFIG;\r
+//\r
+// --------------------------- Serial IRQ Config ------------------------------\r
+//\r
+typedef enum {\r
+ PchQuietMode,\r
+ PchContinuousMode\r
+} PCH_SIRQ_MODE;\r
+///\r
+/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode\r
+///\r
+\r
+typedef struct {\r
+ BOOLEAN SirqEnable; /// Determines if enable Serial IRQ\r
+ PCH_SIRQ_MODE SirqMode; /// Serial IRQ Mode Select\r
+} PCH_LPC_SIRQ_CONFIG;\r
+\r
+///\r
+/// --------------------------- Power Optimizer Config ------------------------------\r
+///\r
+typedef struct {\r
+ UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table\r
+ PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride; /// Pointer to Pci Express devices LTR override table\r
+} PCH_PWR_OPT_CONFIG;\r
+\r
+///\r
+/// --------------------- Low Power Input Output Config ------------------------\r
+///\r
+typedef struct {\r
+ UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled\r
+ UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled\r
+ UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled\r
+ UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled\r
+ UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled\r
+ UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled\r
+ UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled\r
+ UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled\r
+ UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled\r
+ UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled\r
+ UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled\r
+ UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled\r
+ UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled\r
+ UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled\r
+ UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled\r
+ UINT8 Rsvdbits : 2;\r
+} PCH_LPSS_CONFIG;\r
+\r
+///\r
+/// ----------------------------- SCC Config --------------------------------\r
+///\r
+typedef struct {\r
+ UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled\r
+ UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled\r
+ UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled\r
+ UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled\r
+ UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled\r
+ UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5\r
+ UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5\r
+ UINT8 Rsvdbits : 1;\r
+ UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card\r
+ UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card\r
+ UINT8 Rsvdbits1 : 6;\r
+ UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value.\r
+} PCH_SCC_CONFIG;\r
+\r
+///\r
+/// ------------ General PCH Platform Policy protocol definition ------------\r
+///\r
+struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {\r
+ UINT8 Revision;\r
+ UINT8 BusNumber; /// PCI Bus Number of the PCH device\r
+ PCH_DEVICE_ENABLING *DeviceEnabling;\r
+ PCH_USB_CONFIG *UsbConfig;\r
+ PCH_PCI_EXPRESS_CONFIG *PciExpressConfig;\r
+\r
+ PCH_SATA_CONFIG *SataConfig;\r
+ PCH_AZALIA_CONFIG *AzaliaConfig;\r
+ PCH_SMBUS_CONFIG *SmbusConfig;\r
+ PCH_MISC_PM_CONFIG *MiscPmConfig;\r
+ PCH_DEFAULT_SVID_SID *DefaultSvidSid;\r
+ PCH_LOCK_DOWN_CONFIG *LockDownConfig;\r
+ PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;\r
+ PCH_PWR_OPT_CONFIG *PwrOptConfig;\r
+ PCH_LPSS_CONFIG *LpssConfig;\r
+ PCH_SCC_CONFIG *SccConfig;\r
+ UINT8 IdleReserve;\r
+ UINT8 EhciPllCfgEnable;\r
+ UINT8 AcpiHWRed; //Hardware Reduced Mode\r
+};\r
+\r
+#endif\r
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