--- /dev/null
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+ @file\r
+ Spi.h\r
+\r
+ @brief\r
+ This file defines the EFI SPI Protocol which implements the\r
+ Intel(R) ICH SPI Host Controller Compatibility Interface.\r
+\r
+**/\r
+#ifndef _EFI_SPI_H_\r
+#define _EFI_SPI_H_\r
+\r
+\r
+//\r
+#define EFI_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
+ }\r
+#define EFI_SMM_SPI_PROTOCOL_GUID \\r
+ { \\r
+ 0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
+ }\r
+extern EFI_GUID gEfiSpiProtocolGuid;\r
+extern EFI_GUID gEfiSmmSpiProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_SPI_PROTOCOL EFI_SPI_PROTOCOL;\r
+\r
+///\r
+/// SPI protocol data structures and definitions\r
+///\r
+///\r
+/// Number of Prefix Opcodes allowed on the SPI interface\r
+///\r
+#define SPI_NUM_PREFIX_OPCODE 2\r
+\r
+///\r
+/// Number of Opcodes in the Opcode Menu\r
+///\r
+#define SPI_NUM_OPCODE 8\r
+\r
+///\r
+/// Opcode Type\r
+/// EnumSpiOpcodeCommand: Command without address\r
+/// EnumSpiOpcodeRead: Read with address\r
+/// EnumSpiOpcodeWrite: Write with address\r
+///\r
+typedef enum {\r
+ EnumSpiOpcodeReadNoAddr,\r
+ EnumSpiOpcodeWriteNoAddr,\r
+ EnumSpiOpcodeRead,\r
+ EnumSpiOpcodeWrite,\r
+ EnumSpiOpcodeMax\r
+} SPI_OPCODE_TYPE;\r
+\r
+typedef enum {\r
+ EnumSpiCycle20MHz,\r
+ EnumSpiCycle33MHz,\r
+ EnumSpiCycle66MHz, /// Not supported by VLV\r
+ EnumSpiCycle50MHz,\r
+ EnumSpiCycleMax\r
+} SPI_CYCLE_FREQUENCY;\r
+\r
+typedef enum {\r
+ EnumSpiRegionAll,\r
+ EnumSpiRegionBios,\r
+ EnumSpiRegionSeC,\r
+ EnumSpiRegionDescriptor,\r
+ EnumSpiRegionPlatformData,\r
+ EnumSpiRegionMax\r
+} SPI_REGION_TYPE;\r
+\r
+///\r
+/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware\r
+/// Sequencing Commands and Opcode Requirements"\r
+///\r
+typedef enum {\r
+ EnumSpiOperationWriteStatus,\r
+ EnumSpiOperationProgramData_1_Byte,\r
+ EnumSpiOperationProgramData_64_Byte,\r
+ EnumSpiOperationReadData,\r
+ EnumSpiOperationWriteDisable,\r
+ EnumSpiOperationReadStatus,\r
+ EnumSpiOperationWriteEnable,\r
+ EnumSpiOperationFastRead,\r
+ EnumSpiOperationEnableWriteStatus,\r
+ EnumSpiOperationErase_256_Byte,\r
+ EnumSpiOperationErase_4K_Byte,\r
+ EnumSpiOperationErase_8K_Byte,\r
+ EnumSpiOperationErase_64K_Byte,\r
+ EnumSpiOperationFullChipErase,\r
+ EnumSpiOperationJedecId,\r
+ EnumSpiOperationDualOutputFastRead,\r
+ EnumSpiOperationDiscoveryParameters,\r
+ EnumSpiOperationOther,\r
+ EnumSpiOperationMax\r
+} SPI_OPERATION;\r
+\r
+///\r
+/// SPI Command Configuration\r
+/// Frequency The expected frequency to be used (value to be programmed to the SSFC\r
+/// Register)\r
+/// Operation Which Hardware Sequencing required operation this opcode respoinds to.\r
+/// The required operations are listed in EDS Table 5-55: "Hardware\r
+/// Sequencing Commands and Opcode Requirements"\r
+/// If the opcode does not corresponds to any operation listed, use\r
+/// EnumSpiOperationOther, and provides TYPE and Code for it in\r
+/// SpecialOpcodeEntry.\r
+///\r
+typedef struct _SPI_OPCODE_MENU_ENTRY {\r
+ SPI_OPCODE_TYPE Type;\r
+ UINT8 Code;\r
+ SPI_CYCLE_FREQUENCY Frequency;\r
+ SPI_OPERATION Operation;\r
+} SPI_OPCODE_MENU_ENTRY;\r
+\r
+//\r
+// Initialization data table loaded to the SPI host controller\r
+// VendorId Vendor ID of the SPI device\r
+// DeviceId0 Device ID0 of the SPI device\r
+// DeviceId1 Device ID1 of the SPI device\r
+// PrefixOpcode Prefix opcodes which are loaded into the SPI host controller\r
+// OpcodeMenu Opcodes which are loaded into the SPI host controller Opcode Menu\r
+// BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
+// Please note this is a Flash Linear Address, NOT a memory space address.\r
+// This value is platform specific and depends on the system flash map.\r
+// This value is only used on non Descriptor mode.\r
+// BiosSize The the BIOS Image size in flash. This value is platform specific\r
+// and depends on the system flash map. Please note BIOS Image size may\r
+// be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
+// (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
+// placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
+// (in Non Descriptor Mode)\r
+//\r
+typedef struct _SPI_INIT_TABLE {\r
+ UINT8 VendorId;\r
+ UINT8 DeviceId0;\r
+ UINT8 DeviceId1;\r
+ UINT8 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
+ SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
+ UINTN BiosStartOffset;\r
+ UINTN BiosSize;\r
+} SPI_INIT_TABLE;\r
+\r
+//\r
+// Protocol member functions\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_INIT) (\r
+ IN EFI_SPI_PROTOCOL * This,\r
+ IN SPI_INIT_TABLE * InitTable\r
+ );\r
+\r
+/**\r
+\r
+ @brief\r
+ Initializes the host controller to execute SPI commands.\r
+\r
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ @param[in] InitData Pointer to caller-allocated buffer containing the SPI\r
+ interface initialization table.\r
+\r
+ @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
+ @retval EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
+ @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
+ @retval EFI_DEVICE_ERROR Device error, operation failed.\r
+\r
+**/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_LOCK) (\r
+ IN EFI_SPI_PROTOCOL * This\r
+ );\r
+/**\r
+\r
+ @brief\r
+ Initializes the host controller to execute SPI commands.\r
+\r
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ @param[in] InitData Pointer to caller-allocated buffer containing the SPI\r
+ interface initialization table.\r
+\r
+ @retval EFI_SUCCESS Opcode initialization on the SPI host controller completed.\r
+ @retval EFI_ACCESS_DENIED The SPI configuration interface is locked.\r
+ @retval EFI_OUT_OF_RESOURCES Not enough resource available to initialize the device.\r
+ @retval EFI_DEVICE_ERROR Device error, operation failed.\r
+\r
+**/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_EXECUTE) (\r
+ IN EFI_SPI_PROTOCOL * This,\r
+ IN UINT8 OpcodeIndex,\r
+ IN UINT8 PrefixOpcodeIndex,\r
+ IN BOOLEAN DataCycle,\r
+ IN BOOLEAN Atomic,\r
+ IN BOOLEAN ShiftOut,\r
+ IN UINTN Address,\r
+ IN UINT32 DataByteCount,\r
+ IN OUT UINT8 *Buffer,\r
+ IN SPI_REGION_TYPE SpiRegionType\r
+ );\r
+/**\r
+\r
+ @brief\r
+ Execute SPI commands from the host controller.\r
+\r
+ @param[in] This Pointer to the EFI_SPI_PROTOCOL instance.\r
+ @param[in] OpcodeIndex Index of the command in the OpCode Menu.\r
+ @param[in] PrefixOpcodeIndex Index of the first command to run when in an atomic cycle sequence.\r
+ @param[in] DataCycle TRUE if the SPI cycle contains data\r
+ @param[in] Atomic TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
+ @param[in] ShiftOut If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
+ @param[in] Address In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
+ Region, this value specifies the offset from the Region Base; for BIOS Region,\r
+ this value specifies the offset from the start of the BIOS Image. In Non\r
+ Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
+ Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
+ Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
+ supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
+ the flash (in Non Descriptor Mode)\r
+ @param[in] DataByteCount Number of bytes in the data portion of the SPI cycle.\r
+ @param[in] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
+ @param[in] SpiRegionType SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
+ EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
+ Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
+ and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
+ to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
+\r
+ @retval EFI_SUCCESS Command succeed.\r
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.\r
+ @exception EFI_UNSUPPORTED Command not supported.\r
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.\r
+\r
+**/\r
+\r
+///\r
+/// Protocol definition\r
+///\r
+struct _EFI_SPI_PROTOCOL {\r
+ EFI_SPI_INIT Init;\r
+ EFI_SPI_LOCK Lock;\r
+ EFI_SPI_EXECUTE Execute;\r
+};\r
+\r
+#endif\r
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