## @file Vlv2DeviceRefCodePkg.dec\r
#\r
-# Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r
+# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved\r
#\r
# This program and the accompanying materials are licensed and made available under\r
# the terms and conditions of the BSD License that accompanies this distribution.\r
gSeCfTPMPolicyPpiGuid = { 0x4fd1ba49, 0x8f90, 0x471a, {0xa2, 0xc9, 0x17, 0x3c, 0x7a, 0x73, 0x2f, 0xd0}}\r
gEfiPeiReadOnlyVariable2PpiGuid = { 0x2ab86ef5, 0xecb5, 0x4134, {0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4}}\r
gPchPeiInitPpiGuid = { 0xACB93B08, 0x5CDC, 0x4A8F, {0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E}}\r
-\r
+ gPttPassThruPpiGuid = { 0xc5068bac, 0xa7dc, 0x42f1, {0xae, 0x80, 0xca, 0xa2, 0x4b, 0xb4, 0x90, 0x4b}}\r
+ \r
[Protocols]\r
gEfiGlobalNvsAreaProtocolGuid = { 0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}\r
gPpmPlatformPolicyProtocolGuid = { 0xddabfeac, 0xef63, 0x452c, {0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}}\r
gEfiTdtOperationProtocolGuid = {0xfd301ba4, 0x5e62, 0x4679,{ 0xa0, 0x6f, 0xe0, 0x9a, 0xab, 0xdd, 0x2a, 0x91}}\r
gEfiConfigFileNameGuid = { 0x98B8D59B, 0xE8BA, 0x48EE, { 0x98, 0xDD, 0xC2, 0x95, 0x39, 0x2F, 0x1E, 0xDB }}\r
gEfiDFUResultGuid = { 0x14a7c46f, 0xbc02, 0x4047, { 0x9f, 0x18, 0xa5, 0xd7, 0x25, 0xd8, 0xbd, 0x19 }}\r
-\r
+ gPttPassThruProtocolGuid = { 0x73e2576, 0xf6c1, 0x4b91, { 0x92, 0xa9, 0xd4, 0x67, 0x5d, 0xda, 0x34, 0xb1 } }\r
+ \r
[Guids]\r
gEfiCPTokenSpaceGuid = { 0x918211ce, 0xa1d2, 0x43a0, {0xa0, 0x4e, 0x75, 0xb5, 0xbf, 0x44, 0x50, 0x0E}}\r
gEfiSmbusArpMapGuid = { 0x707BE83E, 0x0BF6, 0x40A5, {0xBE, 0x64, 0x34, 0xC0, 0x3A, 0xA0, 0xB8, 0xE2}}\r
gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0|UINT32|0x1000020E\r
gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE|BOOLEAN|0x1000020F\r
gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0|UINT32|0x10000210\r
+ gEfiVLVTokenSpaceGuid.PcdCpuLockBoxDataAddress|0x0|UINT64|0x10000211\r
+ gEfiVLVTokenSpaceGuid.PcdCpuSmramCpuDataAddress|0x0|UINT64|0x10000212\r
+ gEfiVLVTokenSpaceGuid.PcdCpuLockBoxSize|0x0|UINT64|0x10000213\r
\r
[PcdsFeatureFlag]\r
gVlvRefCodePkgTokenSpaceGuid.PcdCeAtaSupport|FALSE|BOOLEAN|0x12\r
gVlvRefCodePkgTokenSpaceGuid.PcdMmcSdMultiBlockSupport|TRUE|BOOLEAN|0x13\r
\r
+[PcdsPatchableInModule]\r
+\r
+ ## Memory Down or DIMM slot.<BR><BR>\r
+ # 0 - DIMM<BR>\r
+ # 1 - Memory Down<BR>\r
+ # @Prompt Enable Memory Down\r
+ # @ValidList 0x80000001 | 0, 1\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1|UINT8|0x20000000\r
+ \r
+ ## Memory Parameter Patchable.<BR><BR>\r
+ # 0 - Fixed Parameter for MinnowBoard Max<BR>\r
+ # 1 - Patchable Parameter for Customization<BR>\r
+ # @Prompt Memory Parameter Patchable.\r
+ # @ValidList 0x80000001 | 0, 1 \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE|BOOLEAN|0x20000010\r
+ \r
+ ## The speed of DRAM.<BR><BR>\r
+ # 0 - 800 MHz<BR>\r
+ # 1 - 1066 MHz<BR>\r
+ # 2 - 1333 MHz<BR>\r
+ # 3 - 1600 MHz<BR>\r
+ # @Prompt DRAM Speed\r
+ # @ValidList 0x80000001 | 0, 1, 2, 3\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1|UINT8|0x20000001\r
+\r
+ ## DRAM Type.<BR><BR>\r
+ # 0 - DDR3<BR>\r
+ # 1 - DDR3L<BR>\r
+ # 2 - DDR3U<BR>\r
+ # 3 - DDR3All<BR>\r
+ # 4 - LPDDR2<BR>\r
+ # 5 - LPDDR3<BR>\r
+ # 6 - DDR4<BR>\r
+ # @Prompt DRAM Type\r
+ # @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1|UINT8|0x20000002\r
+ \r
+ ## Please populate DIMM slot 0 if only one DIMM is supported.<BR><BR>\r
+ # 0 - Disable<BR>\r
+ # 1 - Enable<BR>\r
+ # @Prompt DIMM 0 Enable \r
+ # @ValidList 0x80000001 | 0, 1\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1|UINT8|0x20000003\r
+\r
+ ## DIMM 1 has to be identical to DIMM 0.<BR><BR>\r
+ # 0 - Disable<BR>\r
+ # 1 - Enable<BR>\r
+ # @Prompt DIMM 1 Enable Type\r
+ # @ValidList 0x80000001 | 0, 1\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0|UINT8|0x20000004\r
+ \r
+ ## DRAM device data width.<BR><BR>\r
+ # 0 - x8<BR>\r
+ # 1 - x16<BR>\r
+ # 2 - x32<BR>\r
+ # @Prompt DIMM_DWIDTH\r
+ # @ValidList 0x80000001 | 0, 1, 2\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1|UINT8|0x20000005\r
+\r
+ ## DRAM device data density.<BR><BR>\r
+ # 0 - 1 Gbit<BR>\r
+ # 1 - 2 Gbit<BR>\r
+ # 2 - 4 Gbit<BR>\r
+ # 3 - 8 Gbit<BR>\r
+ # @Prompt DIMM_Density\r
+ # @ValidList 0x80000001 | 0, 1, 2, 3\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2|UINT8|0x20000006\r
+ \r
+ ## DRAM device data bus width.<BR><BR>\r
+ # 0 - 8 bits<BR>\r
+ # 1 - 16 bits<BR>\r
+ # 2 - 32 bits<BR>\r
+ # 3 - 64 bits<BR>\r
+ # @Prompt DIMM_BusWidth\r
+ # @ValidList 0x80000001 | 0, 1, 2, 3\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3|UINT8|0x20000007\r
+\r
+ ## Ranks Per DIMM or Sides Per DIMM.<BR><BR>\r
+ # 0 - 1 Rank<BR>\r
+ # 1 - 2 Ranks<BR>\r
+ # @Prompt DIMM_Sides\r
+ # @ValidList 0x80000001 | 0, 1\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0|UINT8|0x20000008\r
+\r
+ ## tCL.<BR><BR>\r
+ # @Prompt tCL\r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11|UINT8|0x20000009\r
+\r
+ ## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.<BR><BR> \r
+ # @Prompt tRP_tRCD \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11|UINT8|0x2000000A\r
+\r
+ ## tWR in DRAM clk.<BR><BR> \r
+ # @Prompt tWR \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12|UINT8|0x2000000B\r
+ \r
+ ## tWTR in DRAM clk.<BR><BR> \r
+ # @Prompt tWTR \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6|UINT8|0x2000000C\r
+ \r
+ ## tRRD in DRAM clk.<BR><BR> \r
+ # @Prompt tRRD \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6|UINT8|0x2000000D\r
+ \r
+ ## tRTP in DRAM clk.<BR><BR> \r
+ # @Prompt tRTP \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6|UINT8|0x2000000E\r
+\r
+ ## tFAW in DRAM clk.<BR><BR> \r
+ # @Prompt tFAW \r
+ gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32|UINT8|0x2000000F\r
projects / mirror_edk2.git / blobdiff